Abstract

International audience; CMOS technology trends at one side open up some opportunities like making small and power efficient devices available, which in turn allow to put more functionality into a single chip. However, on the other side it poses some challenges like making devices vulnerable to hard and soft errors. In this paper we propose an efficient fault-tolerant architecture able to deal with permanent and transient faults in combinational parts of pipeline structures. The principle consists in triplicating the combinational logic parts but, unlike TMR, only two copies are running in parallel while the third one remains in standby until an error is detected. We implement this approach on a MIPS microprocessor as case study to make it resilient against transient and permanent faults.

Abstract

Data, addresses, and instructions are compressed by maintaining only significant bytes with two or three extension bits appended to indicate the significant byte positions. This significance compression method is integrated into a 5-stage pipeline, with the extension bits flowing down the pipeline to enable pipeline operations only for the significant bytes. Consequently, register logic and cache activity (and dynamic power) are substantially reduced. An initial trace-driven study shows reduction in activity of approximately 30-40% for each pipeline stage. Several pipeline organizations are studied. A byte serial pipeline is the simplest implementation, but suffers a CPI (cycles per instruction) increase of 79% compared with a conventional 32-bit pipeline. Widening certain pipeline stages in order to balance processing bandwidth leads to an implementation with a CPI 24% higher than the baseline 32-bit design. Finally, full-width pipeline stages with operand gating achieve a CPI within 2-6% of the baseline 32-bit pipeline. Peer Reviewed

Abstract

International audience; Increasing vulnerability of transistors and interconnects due to CMOS technology scaling is continuously challenging the reliability of future electronic circuits and systems. Lifetime reliability is gaining attention over performance as a design factor even for lower-end commodity applications. In this paper we propose an effective hybrid fault-tolerant architecture able to deal with permanent and transient faults in combinational parts of pipelined cores. The principle consists in triplicating the combinational logic parts but, unlike TMR, only two copies run in parallel while the third one remains in standby until an error is detected. We have implemented this approach on a MIPS microprocessor as case study. Experiments show that our approach is comparable to TMR in terms of area with a notable power saving and offers a full protection against transient and permanent faults.

Abstract

Electric vehicle battery performance near end-of-life is limited by mismatched cell degradation, leading to an estimated 5-10% cell capacity variation across the pack. Active cell balancing hardware architectures incorporating a Low-Voltage (LV) bus supply have been introduced to unlock lost capacity due to cell imbalance at reduced cost, through elimination of the vehicle's 400-to-12V dc-dc converter. In this work, a hierarchical model-predictive control scheme is applied to a time-shared isolated converter active balancing architecture that incorporates LV bus supply. The proposed controller efficiently divides computation among the battery management system hardware components. The energy-buffering capability of the lead-acid battery, which is connected to the LV bus, is used to trade-off balancing and bus regulation objectives, reducing peak power and improving the system cost-effectiveness. Simultaneous state-of-charge balancing and LV bus regulation is verified in simulation and experiment using real-world drive and LV load data collected from a GM Bolt electric vehicle. Similar controller performance compared to a central scheme is achieved in simulation. The experimental setup includes a custom 12S2P, 3.9kWh, liquid-cooled Lithium Nickel Manganese Cobalt battery module with embedded battery management system. The controller performance is evaluated with an initial maximum state-of-charge imbalance of 6.8%.