Abstract

International audience; This work presents an efficient modification of the classical servo-loop static test setup aimed at the on-chip imple- mentation of reduced-code static linearity test techniques. The proposed modified servo-loop provides a direct measurement of the width of a given ADC code without the need of an integrated voltmeter. The proposed measurement strategy is based on using a controlled step-wise ramp stimulus generator for exciting the ADC under test in such a way that the measurement of a code width can be determined in the digital domain by simply counting the number of ramp steps between two consecutive ADC output transitions. Moreover, the ability of the proposed servo-loop to target a given ADC code makes it very suitable for implementing advanced reduced-code static test techniques. This work analyses the performance limits of the proposed discrete-time servo-loop technique and explores its application to reduced-code linearity testing of pipeline ADCs.

Abstract

International audience; The reduced code linearity test technique for pipeline ADCs consists in measuring some judiciously selected codes which contain the information about the linearity of the converter as opposed to the standard histogram technique that considers indiscriminately all codes. This technique dramatically reduces the static test time for pipeline ADCs. In this paper, we identify some limitations in the existing version of the technique and we provide solutions to enhance its accuracy. The enhanced technique is applied to a 12-bit 2.5-bit/stage pipeline ADC.

Abstract

International audience; This paper introduces a new methodology for evaluating the performance of asynchronous linear-pipelines. The Token Vector Delay Model is introduced to capture delay variability, which can originate from data, process and/or environment. Then, closed form equations modeling handshaking protocols are defined. These equations enable us to construct an abstract analytical model of the pipeline. The analytical model is then solved to compute the circuit performance in the presence of time variable delays. The tool developed to implement the method enables the designer to analyze circuits with tens of pipeline stages in a few seconds.

Abstract

International audience; In nanometer technologies, circuits are more and more sensitive to various kinds of perturbations. Alpha particles and atmospheric neutrons are affecting storage elements as well as the combinational logic. In the past, the major efforts were related on memories. However, as the whole situation is getting worse, solutions that protect the entire design are mandatory. Solutions for detecting the error in logic functions already exist, but there are only few of them that allow the correction, leading to a lot of hardware overhead in non-processor design. In this paper, we present a novel hardware architecture that reduces the cost of rollback in any kinds of circui

Abstract

International audience; This paper introduces a new methodology for determining the minimum number of registers needed to pipeline a linear asynchronous pipeline so that the final cycle time meets some constraints. Moreover, the methodology defines the optimum placing for the registers; ends with an optimally pipelined circuit.

Abstract

International audience; Reliability evaluation is a critical task in computing systems. From one side, the results must be accurate enough not to under-or over-estimate the overall system reliability (thus either resulting in a non-reliable system, or a system for which too expensive solutions have been adopted). On the other side, the time required for the analysis should be kept at the minimum. This paper presents some new advances in the reliability assessment of computing systems, by showing techniques targeting both hardware and software levels, and the combination of both.