Abstract

International audience; Burn-In (BI) test is usually applied in manufacturing process to screen out chip early life failures, especially for safety critical applications. Unfortunately, this test method has elevated costs for companies. In recent days, Faster-than-at-Speed-Test (FAST) has become a useful technique to discover small delay defects. At the same time, overclocking methods to enhance system performances have been studied, which focus on temperature management to preserve system functionalities. In this paper, a FAST technique is approached with the aim of intentionally provoking a thermal overheating in the microprocessor by mean of the execution of functional test programs, partly regardless of system behavior preservation. The goal is to introduce an internal stress stronger than current procedures used during BI in order to speed up early detection of latent faults. The method illustrates how to avoid blocking configurations due to timing constraints violation and leads to a significant increase of the switching activity. Experimental results on a MIPS architecture show that, by using the described technique, the processor is not falling into an unpredictable state even at frequencies up to about 20 times higher than the nominal one and the switching activity is increasing up to 300% per nanoseconds.

Abstract

ISBN : 978-1-4244-2182-4; International audience; This paper introduces a new methodology for optimizing the performance of Asynchronous-Linear Pipelines. The method supports all delay types, static and variable time delays, enabling the designers to optimize their architecture taking into account the timing information of data dependencies, circuit structure and process variations. The method not only determines the minimum degree of pipelining necessary to satisfy a given performance target, but also computes the optimum placement of the pipeline stages to maximize the throughput.

Abstract

International audience; This work presents an efficient modification of the classical servo-loop static test setup aimed at the on-chip imple- mentation of reduced-code static linearity test techniques. The proposed modified servo-loop provides a direct measurement of the width of a given ADC code without the need of an integrated voltmeter. The proposed measurement strategy is based on using a controlled step-wise ramp stimulus generator for exciting the ADC under test in such a way that the measurement of a code width can be determined in the digital domain by simply counting the number of ramp steps between two consecutive ADC output transitions. Moreover, the ability of the proposed servo-loop to target a given ADC code makes it very suitable for implementing advanced reduced-code static test techniques. This work analyses the performance limits of the proposed discrete-time servo-loop technique and explores its application to reduced-code linearity testing of pipeline ADCs.

Abstract

International audience; The reduced code linearity test technique for pipeline ADCs consists in measuring some judiciously selected codes which contain the information about the linearity of the converter as opposed to the standard histogram technique that considers indiscriminately all codes. This technique dramatically reduces the static test time for pipeline ADCs. In this paper, we identify some limitations in the existing version of the technique and we provide solutions to enhance its accuracy. The enhanced technique is applied to a 12-bit 2.5-bit/stage pipeline ADC.

Abstract

ISBN : 978-1-4244-2182-4; International audience; Fault-injection based dependability analysis has proved to be an efficient mean to predict the behavior of a circuit in presence of faults. Emulation-based approaches enable fast and flexible analyses of significant designs such as processors running significant application software. This paper presents the results obtained with an encryption application and questions the usefulness and the effectiveness of detection mechanisms in both hardware and software.

Abstract

Side-Channel Attacks (SCAs) present a serious threat to the security of crypto-systems. In this paper, we show how a pipelined embedded processor opens the door to such attacks. To illustrate our approach, a concrete evaluation of the Xilinx’s MicroBlaze soft-core processor is conducted. From these results, we suggest a new masking countermeasure suited for RISC-based architectures. The efficiency and limits of the proposed solution are finally evaluated.

Abstract

To protect against hardware fault attacks, developers can use software countermeasures. They are generally designed to thwart software fault models such as instruction skip or memory corruption. However, these typical models do not take into account the actual implementation of a processor. By analyzing the processor microarchitecture, it is possible to bypass typical software countermeasures. In this paper, we analyze the vulnerability of a secure code from FISSC (Fault Injection and Simulation Secure Collection), by simulating fault injections in a RISC-V Rocket processor RTL description. We highlight the importance of hidden registers in the processor pipeline, which temporarily hold data during code execution. Secret data can be leaked by attacking these hidden registers. Software countermeasures against such attacks are also proposed.

Abstract

International audience; Adiabatic logic is an alternative architecture design style to reduce the power consumption of digital cores by using AC power supply instead of DC ones. The energy saving of the digital gates is strongly related to the efficiency of adiabatic AC power supplies. In this paper, we propose a resonant reversible power-clock supply design with four different phases. The resonance deviation between the four power-clock supplies is synchronized thanks to 12 control signals (3 controls signals per power-clock supply). We derive the energy dissipation of a 4-stage PFAL pipeline circuit supplied with the proposed resonant powerclock supply, which can dissipate up to 2.9 times less energy than a non-adiabatic CMOS pipeline.

Abstract

International audience; Testing analog, mixed-signal and RF circuits rep- resents the main cost component for testing complex SoCs. A promising solution to alleviate this cost is the machine learning- based test strategy. These test techniques are an indirect test approach that replaces costly specification measurements by simpler signatures. Machine learning algorithms are used to map these signatures to the performance parameters. Although this approach has a number of undoubtable advantages, it also opens new issues that have to be addressed before it can be widely adopted by the industry. In this paper we present a machine learning-based test for a complex mixed-signal system –i.e. a state-of-the-art pipeline ADC– that includes digital calibration. This paper shows how the introduction of digital calibration for the ADC has a serious impact in the proposed test as calibration completely decorrelates signatures from the target specification in the presence of local mismatch.

Abstract

International audience; This paper introduces a new methodology for evaluating the performance of asynchronous linear-pipelines. The Token Vector Delay Model is introduced to capture delay variability, which can originate from data, process and/or environment. Then, closed form equations modeling handshaking protocols are defined. These equations enable us to construct an abstract analytical model of the pipeline. The analytical model is then solved to compute the circuit performance in the presence of time variable delays. The tool developed to implement the method enables the designer to analyze circuits with tens of pipeline stages in a few seconds.