Static timing analysis for hard real-time systems

Abstract

Hard real-time systems have to satisfy strict timing constraints. To prove that these constraints are met, timing analyses aim to derive safe upper bounds on tasks’ execution times. Processor components such as caches, out-of-order pipelines, and speculation cause a large variation of the execution time of instructions, which may induce a large variability of a task’s execution time. The architectural platform also determines the precision and the complexity of timing analysis. This paper provides an overview of our timing-analysis technique and in particular the methodological aspects of interest to the verification community.

Original document

The different versions of the original document can be found in:

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• http://link.springer.com/content/pdf/10.1007/978-3-642-11319-2_3.pdf,

http://dx.doi.org/10.1007/978-3-642-11319-2_3

• https://opus.bibliothek.uni-augsburg.de/opus4/frontdoor/index/index/docId/69878,

https://doi.org/10.1007/978-3-642-11319-2_3