Abstract

It was around the years 2003 to 2005 that a dramatic change seized the semiconductor industry and the manufactures of processors. The increasing of computing performance in processors, based on simply screwing up the clock frequency, could not longer be holded. All the years before the clock frequency could be steadily increased by improvements achieved both on technology and on architectural side. Scaling of the technology processes, leading to smaller channel lengths and shorter switching times in the devices, and measures like instruction-level-parallelism and out-of-order processing, leading to high fill rates in the processor pipelines, were the guarantors to meet Moore’s law.


Original document

The different versions of the original document can be found in:

http://dx.doi.org/10.5772/38478
https://nbn-resolving.org/urn:nbn:de:bvb:29-opus-35857,
https://opus4.kobv.de/opus4-fau/files/2409/schmidt_parallel_3585.pdf
https://cdn.intechopen.com/pdfs/31912/InTech-Parallel_embedded_computing_architectures.pdf,
https://academic.microsoft.com/#/detail/1501549827
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Published on 01/01/2012

Volume 2012, 2012
DOI: 10.5772/38478
Licence: Other

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