International audience; In a software development lifecycle, it is often more than half of the development time that is dedicated to verification activities. Formal methods offer new possibilities for verification. In the specification phase, simulation or model-checking allow users to detect errors in models. In the implementation phase, analysis techniques, like static analysis, make the verification tasks more exhaustive and more automatic. In this context, we propose to take advantage of these methods to improve embedded software development processes based on the V-model.

Document type: Part of book or chapter of book

Original document

The PDF file did not load properly or your web browser does not support viewing PDF files. Download directly to your device: Download PDF document The different versions of the original document can be found in:
Back to Top

Document information

Published on 01/01/2012

Volume 2012, 2012
DOI: 10.1007/978-3-642-33609-6_16
Licence: CC BY-NC-SA license

Document Score


Views 1
Recommendations 0

Share this document

claim authorship

Are you one of the authors of this document?