A Macro-Model for the Efficient Simulation of an ADC-based RNG

Abstract

We present a macro-model for a true random number generator which internally exploits a pipeline analog-to-digital converter modified to operate as an interleaved chaotic map. The model is tuned to reproduce the non-idealities of a 0.35 /spl mu/m CMOS double-poly triple-metal technology. It is based on circuit-level simulations but is extremely more efficient and can be used to run the statistical tests that assure the quality of the output stream.

Original document

The different versions of the original document can be found in:

• http://hdl.handle.net/11583/2850181

• http://hdl.handle.net/11585/7686

• http://xplorestaging.ieee.org/ielx5/9898/31469/01465594.pdf?arnumber=1465594,

http://dx.doi.org/10.1109/iscas.2005.1465594

• https://dblp.uni-trier.de/db/conf/iscas/iscas2005-5.html#PareschiSR05,

https://academic.microsoft.com/#/detail/2106317593