Fine-grain pipelined asynchronous adders for high-speed DSP applications

Abstract

new asynchronous pipeline scheme (called LP/sub w/), and two new pipelined asynchronous adder implementations, are introduced for high-throughput applications such as DSPs for multimedia processing. The pipeline scheme is targeted to dynamic datapaths. A novelty of the approach is that it uses decoupled control for pull-up and pull-down stacks. The adders are pipelined at the gate-level and achieve very high throughput: 930-1023 million additions per second in a 0.6/spl mu/ CMOS process. These results are expected to scale to several gigaoperations per second in more modern technologies.

Original document

The different versions of the original document can be found in:

• http://www.cs.unc.edu/~montek/pubs/singh-nowick-wvlsi2000.pdf

• http://www.cs.unc.edu/~montek/pubs/singh-nowick-wvlsi2000.pdf,

https://dl.acm.org/citation.cfm?id=556628.838093,

https://www1.cs.columbia.edu/async/publications/singh-nowick-wvlsi2000.pdf,

http://www.cs.columbia.edu/async/publications/singh-nowick-wvlsi2000.pdf,

https://academic.microsoft.com/#/detail/2152339026

• http://xplorestaging.ieee.org/ielx5/6799/18244/00844538.pdf?arnumber=844538,

http://dx.doi.org/10.1109/iwv.2000.844538