Logic synthesis for better than worst-case designs

Abstract

In this paper we present a novel metric for measuring and optimizing the performance of circuits that operate with the clock period smaller than the worst-case delay. In particular, we developed an efficient logic optimization operation “balance” and a library mapping algorithm named BTWLibMap. Together they are able to reduce the probability of a timing error by 2.3X while only incurring a 4% area overhead.

Original document

The different versions of the original document can be found in:

• http://ballade.cs.ucla.edu/~cong/papers/vlsi-dat_final_v5.pdf

• http://cadlab.cs.ucla.edu/%7Econg/papers/vlsi-dat_final_v5.pdf,

http://yadda.icm.edu.pl/yadda/element/bwmeta1.element.ieee-000005158121,

https://academic.microsoft.com/#/detail/2134165615

• http://xplorestaging.ieee.org/ielx5/5128899/5158074/05158121.pdf?arnumber=5158121,

http://dx.doi.org/10.1109/vdat.2009.5158121