Abstract

Overclocking a CPU is a common practice among home-built PC enthusiasts where the CPU is operated at a higher frequency than its speed rating. This practice is unsafe because timing errors cannot be detected by modern CPUs and they can be practically undetectable by the end user. Using a timing speculation technique such as Razor, it is possible to detect timing errors in CPUs. To date, Razor has been shown to correct only unidirectional, feed-forward processor pipelines. In this paper, we safely overclock 2D arrays by extending Razor correction to cover bidirectional communication in a tightly coupled or lockstep fashion. To recover from an error, stall wavefronts are produced which propagate across the device. Multiple errors may arise in close proximity in time and space; if the corresponding stall wavefronts collide, they merge to produce a single unified wavefront, allowing recovery from multiple errors with one stall cycle. We demonstrate the correctness and viability of our approach by constructing a proof-of-concept prototype which runs on a traditional Altera FPGA. Our approach can be applied to custom computing arrays, systolic arrays, CGRAs, and also time-multiplexed FPGAs such as those produced by Tabula. As a result, these devices can be overclocked and safely tolerate dynamic, data-dependent timing errors. Alternatively, instead of overclocking, this same technique can be used to `undervolt' the power supply and save energy.


Original document

The different versions of the original document can be found in:

https://dblp.uni-trier.de/db/conf/fccm/fccm2013.html#BrantASTYL13,
https://dl.acm.org/citation.cfm?id=2495653,
https://ieeexplore.ieee.org/document/6545992,
https://academic.microsoft.com/#/detail/2067418954
http://dx.doi.org/10.1109/fccm.2013.63
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Document information

Published on 01/01/2013

Volume 2013, 2013
DOI: 10.1109/fccm.2013.63
Licence: CC BY-NC-SA license

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