Implementing latency-insensitive dataflow blocks

Abstract

To simplify the implementation of dataflow systems in hardware, we present a technique for designing latency- insensitive dataflow blocks. We provide buffering with backpressure, resulting in blocks that compose into deep, high-speed pipelines without introducing long combinational paths. Our input and output buffers are easy to assemble into simple unit- rate dataflow blocks, arbiters, and blocks for Kahn networks. We prove the correctness of our buffers, illustrate how they can be used to assemble arbitrary dataflow blocks, discuss pitfalls, and present experimental results that suggest our pipelines can operate at a high clock rate independent of length.

Original document

The different versions of the original document can be found in:

• http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.696.1516

• http://www.cs.columbia.edu/~sedwards/papers/cao2015implementing.pdf,

https://dblp.uni-trier.de/db/conf/memocode/memocode2015.html#CaoRKE15,

https://academic.microsoft.com/#/detail/2183333258

• http://xplorestaging.ieee.org/ielx7/7329076/7340456/07340485.pdf?arnumber=7340485,

http://dx.doi.org/10.1109/memcod.2015.7340485