Abstract

International audience; The xMAS micro-architecture modeling language has been introduced by Intel to facilitate the formal representation and analysis of on-chip interconnect fabrics. In this paper, we introduce xMAStime, a new domain-specific language inspired by xMAS. xMAStime allows the modeling of full micro-architectures comprising certain classes of CPU pipelines, caches, and RAM. Given an in-order pipeline model in xMAStime, we automatically generate both a Cycle-Accurate, Bit-Accurate (CABA) hardware simulator and a timed instruction set simulator where time is accounted with safe upper bounds, as in the pipeline analysis step of Worst-Case Execution Time (WCET) analysis. The approach relies on the theory of endochronous systems, which allows us to ensure functional equivalence and timing consistency between the two generated simulators, using a delay-insensitivity argument. xMAStime is implemented over Lucid Synchrone-a dataflow synchronous language featuring a higher order type system and type inference, which facilitate the definition of our DSL. We use the new DSL to model and synthesize simulation code for a full-fledged MIPS32-based architecture.


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The different versions of the original document can be found in:

http://dx.doi.org/10.1109/acsd.2018.00019
https://academic.microsoft.com/#/detail/2900736265
https://hal.inria.fr/hal-01959370/document,
https://hal.inria.fr/hal-01959370/file/main.pdf
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Published on 01/01/2018

Volume 2018, 2018
DOI: 10.1109/acsd.2018.00019
Licence: CC BY-NC-SA license

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