Process variation has become a major concern in the design of many nanometer circuits, including interconnect pipelines. This paper develops closed-form models to predict the delay distribution of an interconnect pipeline stage and the slew distributions of all the nets in the circuit. Also, a buffer sizing and re-placement algorithm is presented to minimize the area of interconnect pipelines while meeting the delay and slew constraints. Experiments show that ignoring location dependent variation can cause a timing yield loss of 8.8% in a delay limited circuit, and the area can be improved by over 10% when the location dependent variation and residual random variation are understood and separated. Furthermore, under equivalent area, an interconnect pipeline optimized with only sizing changes may violate the slew constraint on over 50% of the nets, so location change is needed to best optimize these circuits.
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