In this paper, a tool to aid pipelined processor instruction set implementation is described. The purpose of the tool is to choose from among design alternatives a design that minimizes overall processor cost. In the proposed cost model processor cost has two components, the cost of hardware necessary to realize the processor and the cost of degraded performance due to pipeline hazards as compared to an ideal pipelined processor. The tool user provides several alternate hardware implementations of each instruction, the cost of hardware operators used, a trade-off factor representing the relative importance of hardware cost versus degraded performance cost, and a straight line benchmark program which is used by the tool to determine frequency of occurrence of pairs of instructions. Using a linear programming approach, the tool selects an implementation for each instruction which gives an overall cost which is optimal.

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Published on 01/01/2003

Volume 2003, 2003
DOI: 10.1145/196244.196526
Licence: CC BY-NC-SA license

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