Latest revision as of 22:59, 28 January 2021

Abstract

Debugging design errors is a challenging manual task which requires the analysis of long simulation traces. Trace compaction techniques help engineers analyze the cause of the problem by reducing the length of the trace. This work presents an optimal error trace compaction technique based on incremental SAT. The approach builds a SAT instance from the Iterative Logic Array representation of the circuit and performs a binary search to find the minimum trace length. Since failing properties in the original trace must be maintained in the compacted trace, we enrich our formulation with constraints to guarantee property preservation. Extensive experiments show the effectiveness out SAT based approach as it preserves failing properties with little overhead to the SAT problem while demonstrating on average an order of magnitude in performance improvement.

Original document

The different versions of the original document can be found in:

• http://www.eecg.utoronto.ca/~veneris/9mid.pdf

• http://xplorestaging.ieee.org/ielx5/5230480/5235877/05235932.pdf?arnumber=5235932,

http://dx.doi.org/10.1109/mwscas.2009.5235932

• https://www.eecg.utoronto.ca/~veneris/9mid.pdf,

http://www.eecg.toronto.edu/~veneris/9mid.pdf,

http://yadda.icm.edu.pl/yadda/element/bwmeta1.element.ieee-000005235932,

https://ieeexplore.ieee.org/document/5235932,

https://academic.microsoft.com/#/detail/2171368936