Latest revision as of 01:12, 2 February 2021

Abstract

Trabajo presentado al 22nd PATMOS celebrado en Newcastle del 4 al 6 de septirmbre de 2012.

Monostable to Bistable (MOBILE) gates are very suitable for the implementation of gate-level pipelines which can be achieved without resorting to memory elements. MOBILE operating principle is implemented using two series connected Negative Differential Resistance (NDR) devices with a clocked bias. This paper describes and experimentally validates a two-phase clock scheme for such MOBILE based ultra-grain pipelines. Up to our knowledge it is the first MOBILE working circuit reported with this interconnection architecture. The proposed interconnection architecture is applied to the design of a 4-bit Carry Look-ahead Adder.

This work has been funded by Ministerio de Economía y Competitividad del Gobierno de España with support from ERDF under Project TEC2010-18937.

Peer Reviewed

Original document

The different versions of the original document can be found in:

• http://hdl.handle.net/10261/84521

• https://digital.csic.es/bitstream/10261/84521/4/Two-phase%20MOBILE.pdf

• http://digital.csic.es/bitstream/10261/84521/4/Two-phase%20MOBILE.pdf,

https://digital.csic.es/handle/10261/84521,

https://www.scipedia.com/public/Nunez_et_al_2013a,

https://dblp.uni-trier.de/db/conf/patmos/patmos2012.html#NunezAQ12,

https://digital.csic.es/bitstream/10261/84521/4/Two-phase%20MOBILE.pdf,

https://rd.springer.com/chapter/10.1007/978-3-642-36157-9_17,

https://link.springer.com/chapter/10.1007%2F978-3-642-36157-9_17,

https://academic.microsoft.com/#/detail/76295343

• http://www.springerlink.com/index/pdf/10.1007/978-3-642-36157-9_17,

http://dx.doi.org/10.1007/978-3-642-36157-9_17