J. Goes, R. Tavares, A. Galhardo, M. Silva, N. Paulino, B. Esperanca
IEEE International Symposium on Circuits and Systems, pp. 220 – 223, Seattle, EUA This paper presents a 14-bit 1.5 MSample/s two-stage algorithmic ADC with a power-and-area efficiency better than 0.5 pJmm2 per conversion. This competes with the most efficient architectures available today namely, ΣΔ and self-calibrated pipeline. The 2 stages of the ADC are based on a new 1.5-bit mismatch-insensitive MDAC and simulations demonstrate that a THD of –79 dB and an ENOB better than 12 bits can be reached without self-calibration.
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Published on 01/01/2008
Volume 2008, 2008DOI: 10.1109/iscas.2008.4541394Licence: CC BY-NC-SA license
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