Virtual Pipelining allows designs of arbitrary size to execute on finite sized FPGA devices. It allows pipelined designs to be efficiently configured on a FPGA by overlapping the reconfiguration time of a pipeline stage with the execution time of previous pipeline stages. This technique produces performance improvement up to an order of 5 versus a non-pipelined execution of a design. We extend this principle for handling large designs that were previously too large to fit on an FPGA. This paper presents a framework for automatically synthesizing virtual pipelines on an Virtex FPGA. We also suggest criteria for extending our approach to non-Virtex FPGAs.
The different versions of the original document can be found in:
Published on 01/01/2003
Volume 2003, 2003
DOI: 10.1109/aspdac.2002.994943
Licence: CC BY-NC-SA license
Are you one of the authors of this document?