1.2V 10bit 83MS/s pipeline ADC implemented in 130nm CMOS Technology is described with practical design techniques and considerations. Emphasis was placed on noise analysis and capacitance optimization, which helps to reduce both die area and power consumption. Design experiences of operational amplifier, comparator and switches were also shared. This design achieves INL and DNL of +0.65/-0.53LSB and +0.33/-0.33LSB respectively, while SNDR is 57.7dB.
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Published on 31/12/10
Accepted on 31/12/10
Submitted on 31/12/10
Volume 2011, 2011
DOI: 10.1109/uksim.2011.107
Licence: CC BY-NC-SA license
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