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Abstract

15th IEEE International Conference on Electronics, Circuits and Systems, Malta In this paper a new time-interleaved 1.5-bit MDAC circuit is proposed. This circuit is well suited to be used in ultra low-power high-speed 4-to-8 bits pipeline ADCs. The required gain of two is implemented by switching a MOS capacitor from inversion into depletion within a clock-cycle. Low-power is achieved since no operational amplifiers are required but, instead, simple source-followers are used. Simulation results of a complete front-end stage of a 6-bit 2-channel pipeline ADC demonstrate the efficiency of the proposed technique.


Original document

The different versions of the original document can be found in:

http://dx.doi.org/10.1109/icecs.2008.4674838
http://yadda.icm.edu.pl/yadda/element/bwmeta1.element.ieee-000004674838,
https://dblp.uni-trier.de/db/conf/icecsys/icecsys2008.html#OliveiraGPFP08,
https://run.unl.pt/handle/10362/4057,
https://ieeexplore.ieee.org/document/4674838,
https://academic.microsoft.com/#/detail/2156077706
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Document information

Published on 01/01/2008

Volume 2008, 2008
DOI: 10.1109/icecs.2008.4674838
Licence: CC BY-NC-SA license

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