== Abstract ==

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In this paper, we propose a 4/spl times/4-block level pipelining architecture with instantaneous switching scheme and optimal decoding ordering of H.264/AVC decoder. Compared with conventional H.264/AVC video decoders, which adopt macroblock level pipelines, our proposed 4/spl times/4-block level pipelining architecture of H.264/AVC decoder achieves better hardware utilization. Moreover, our proposed decoding ordering can effectively save memory access and reduce processing cycles, which results in 260000 MB/s under 100 MHz clock frequency. By adopting these two techniques, our proposed design supports real time decoding with 1080HD (1920/spl times/1088) video sequence in 30fps (244800 MB/s required) and level 4 of baseline profile.

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== Original document ==

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The different versions of the original document can be found in:

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* [http://www.si2lab.org/publications/cnf/talin_iscas05.pdf http://www.si2lab.org/publications/cnf/talin_iscas05.pdf]

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* [http://xplorestaging.ieee.org/ielx5/9898/31469/01464961.pdf?arnumber=1464961 http://xplorestaging.ieee.org/ielx5/9898/31469/01464961.pdf?arnumber=1464961],

: [http://dx.doi.org/10.1109/iscas.2005.1464961 http://dx.doi.org/10.1109/iscas.2005.1464961]

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* [https://dblp.uni-trier.de/db/conf/iscas/iscas2005-2.html#LinWLL05 https://dblp.uni-trier.de/db/conf/iscas/iscas2005-2.html#LinWLL05],

: [https://ir.nctu.edu.tw:443/handle/11536/17765 https://ir.nctu.edu.tw:443/handle/11536/17765],

: [http://www.si2lab.org/publications/cnf/talin_iscas05.pdf?origin=publication_detail http://www.si2lab.org/publications/cnf/talin_iscas05.pdf?origin=publication_detail],

: [https://academic.microsoft.com/#/detail/1495620715 https://academic.microsoft.com/#/detail/1495620715]

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