Abstract

International audience; With the rapid size shrinking in electronic devices,radiation-induced soft-error has emerged as a major concern to the current circuit manufacturing. In this paper, we present a new error correction scheme based on the residue number arithmetic to cope with the single soft-error issue. The proposed technique called bidirectional redundant residue number system requires the redundant moduli to satisfy some constraints to achieve fast error correction. In this system, both the iterations for decoding the valid number and the error-correcting table that contains all combinations of erroneous digit, are not necessary. The detection and the diagnosis are simultaneously performed in plural parallel consistent-checking that has the capability of locating the corrupt digit. Finally, efficient pipeline architecture for the self-diagnosis decoder is detailed.

Abstract

Submitted on behalf of EDAA (http://www.edaa.com/); International audience; The wider and wider use of high-performance processors as part of real-time systems makes it more and more difficult to guarantee that programs will respect their strict deadlines. While the computation of Worst-Case Execution Times relies on static analysis of the code, the challenge is to model with enough safety and accuracy the behaviour of intrisically dynamic components. In this paper, we focus on the dynamic branch predictor. Several models to bound the number of branch mispredictions have been previously published. Some of them exhibit a high complexity while other ones have shown that taking into account semantic information from the source code makes things more tractable. We extend this work to more general nested loop structures. We also give some simulation results that show that the way branch mispredictions are usually taken into account cannot be both safe and accurate in the case of high-performance pipelines. We propose a more realistic approach to be used as part of WCET computation.

Abstract

International audience; The present paper focuses on wireless energy transfer mechanisms applied to urban electric vehicles. It describes the using conditions of a particular transformer without ferromagnetic core, supplied by a resonant inverter and loaded by mobile sources (catenaries with magnetic induction to power electric vehicles). The system consists of unconventional transformers with large air-gaps and a generator who supplies the transformer. The paper describes the theoretical model used for the numerical simulation (magnetic circuit, power converter, loads), and the measurements provided by our experimental platform (Tesla lab.). The transformer is supplied by a half-bridge series resonant converter. The transformer secondary coil is mobile compared to the primary, which is fixed on the road. This system is found in many industrial applications such as light automatic vehicles, tramways, etc. In this work we will show that the performance of a transformer without magnetic circuit can be equivalent to a standard transformer.

Abstract

For an open-end windings integrated Permanent Magnet Synchronous Machine, the demagnetization of the permanent magnets is analyzed when a transistor is short-circuited and no specific control strategy is adopted. Depending on the temperature, the high currents due to the inverter fault may locally demagnetized the permanent magnets leading to an accelerated aging of the machine and torque loss. A co-simulation, using a Finite Element software for the machine coupled with an average modeling of the transistor, gives interesting local prediction of the machine behavior in healthy and degraded mode. This work has been achieved within the framework of CE2I project. CE2I is co-financed by European Union with the financial support of European Regional Development Fund (ERDF), French State and the French Region of Hauts-de-France.

Abstract

The emerging concept of SoC-AMS leads to research new top-down methodologies to aid systems designers in sizing analog and mixed devices. This work applies this idea to the high-level optimization of pipeline ADC. Considering a given technology, it consists in comparing different configurations according to their imperfections and their architectures without FFT computation or time-consuming simulations. The final selection is based on a figure of merit. Comment: Submitted on behalf of EDAA (http://www.edaa.com/)

Abstract

Operating frequency of a pipelined circuit is determined by the delay of the slowest pipeline stage. However, under statistical delay variation in sub-100nm technology regime, the slowest stage is not readily identifiable and the estimation of the pipeline yield with respect to a target delay is a challenging problem. We have proposed analytical models to estimate yield for a pipelined design based on delay distributions of individual pipe stages. Using the proposed models, we have shown that change in logic depth and imbalance between the stage delays can improve the yield of a pipeline. A statistical methodology has been developed to optimally design a pipeline circuit for enhancing yield. Optimization results show that, proper imbalance among the stage delays in a pipeline improves design yield by 9% for the same area and performance (and area reduction by about 8.4% under a yield constraint) over a balanced design. Comment: Submitted on behalf of EDAA (http://www.edaa.com/)

Abstract

International audience; In this paper, we propose a video streaming architecture implementing an IP core design based on Histograms of Oriented Gradients (HOG) algorithm, by using a high-level synthesis workflow. Also, we present a decision algorithm for a dynamically reconfigurable architecture, applied to people detection in video over a Region Of Interest (ROI). Our method dynamically manages the resource consumption in our hardware accelerator. In the test performed with only one reconfigurable module, our method achieves a power reduction up to 7% and a speed of 51 fps, but these results could be improved according to the number of reconfigurable modules. For implementation, we used a Xilinx Zynq 7000 series platform and our experimental results are compared with other software and hardware implementations. Our hardware architecture can be used in a vast number of vision systems, including advanced driver assistance systems (ADAS).

Abstract

Detailed modeling of processors and high performance cycle-accurate simulators are essential for today's hardware and software design. These problems are challenging enough by themselves and have seen many previous research efforts. Addressing both simultaneously is even more challenging, with many existing approaches focusing on one over another. In this paper, we propose the Reduced Colored Petri Net (RCPN) model that has two advantages: first, it offers a very simple and intuitive way of modeling pipelined processors; second, it can generate high performance cycle-accurate simulators. RCPN benefits from all the useful features of Colored Petri Nets without suffering from their exponential growth in complexity. RCPN processor models are very intuitive since they are a mirror image of the processor pipeline block diagram. Furthermore, in our experiments on the generated cycle-accurate simulators for XScale and StrongArm processor models, we achieved an order of magnitude (~15 times) speedup over the popular SimpleScalar ARM simulator. Comment: Submitted on behalf of EDAA (http://www.edaa.com/)

Abstract

Submitted on behalf of EDAA (http://www.edaa.com/); International audience; While most of the effort in improving verification times for pipeline machine verification has focused on faster decision procedures, we show that the refinement maps used also have a drastic impact on verification times. We introduce a new class of refinement maps for pipelined machine verification, and using the state-of-the-art verification tools UCLID and Siege we show that one can attain several orders of magnitude improvements in verification times over the standard flushing-based refinement maps, even enabling the verification of machines that are too complex to otherwise automatically verify.