Scipediacontent: Scipediacontent moved page Draft Content 538420718 to Torres et al 2009a

2021-02-16T09:26:43Z

Scipediacontent moved page Draft Content 538420718 to Torres et al 2009a

Scipediacontent: Created page with " == Abstract == This paper focuses on how to design a store buffer (STB) well suited to first-level multibanked data caches. The goal is to forward data from in-flight stores..."

2021-02-16T09:26:35Z

Created page with " == Abstract == This paper focuses on how to design a store buffer (STB) well suited to first-level multibanked data caches. The goal is to forward data from in-flight stores..."

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== Abstract ==

This paper focuses on how to design a store buffer (STB) well suited to first-level multibanked data caches. The goal is to forward data from in-flight stores into dependent loads within the latency of a cache bank. Taking into account the store lifetime in the processor pipeline and the data forwarding behavior, we propose a particular two-level STB design in which forwarding is done speculatively from a distributed first-level STB made of extremely small banks, whereas a centralized, second-level STB enforces correct store-load ordering. Besides, the two-level STB admits two simplifications that leave performance almost unchanged. Regarding the second-level STB, we suggest to remove its data forwarding capability, while for the first-level STB, it is possible to: 1) remove the instruction age checking and 2) compare only the less significant address bits. Experimentation covers both integer and floating point codes executing in dynamically scheduled processors. Following our guidelines and running SPEC-2K over an 8-way processor, a two-level STB with four 8-entry banks in the first level performs similar to an ideal, single-level STB with 128-entry banks working at the first-level cache latency. Also, we show that the proposed two-level design is suitable for a memory-latency-tolerant processor.

== Original document ==

The different versions of the original document can be found in:

* [http://dx.doi.org/10.1109/TC.2009.57 http://dx.doi.org/10.1109/TC.2009.57]

* [http://webdiis.unizar.es/gaz/biblio/pdfs/Torres2009.pdf http://webdiis.unizar.es/gaz/biblio/pdfs/Torres2009.pdf]

* [http://xplorestaging.ieee.org/ielx5/12/5226180/04815214.pdf?arnumber=4815214 http://xplorestaging.ieee.org/ielx5/12/5226180/04815214.pdf?arnumber=4815214],
: [http://dx.doi.org/10.1109/tc.2009.57 http://dx.doi.org/10.1109/tc.2009.57]

* [https://dblp.uni-trier.de/db/journals/tc/tc58.html#TorresIYL09 https://dblp.uni-trier.de/db/journals/tc/tc58.html#TorresIYL09],
: [http://yadda.icm.edu.pl/yadda/element/bwmeta1.element.ieee-000004815214 http://yadda.icm.edu.pl/yadda/element/bwmeta1.element.ieee-000004815214],
: [https://ieeexplore.ieee.org/document/4815214 https://ieeexplore.ieee.org/document/4815214],
: [https://dl.acm.org/citation.cfm?id=1608711 https://dl.acm.org/citation.cfm?id=1608711],
: [https://www.computer.org/csdl/trans/tc/2009/10/ttc2009101307.pdf https://www.computer.org/csdl/trans/tc/2009/10/ttc2009101307.pdf],
: [https://academic.microsoft.com/#/detail/2140298077 https://academic.microsoft.com/#/detail/2140298077]

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Torres et al 2009a - Revision history

Scipediacontent: Scipediacontent moved page Draft Content 538420718 to Torres et al 2009a

Scipediacontent: Created page with " == Abstract == This paper focuses on how to design a store buffer (STB) well suited to first-level multibanked data caches. The goal is to forward data from in-flight stores..."