Scipediacontent: Scipediacontent moved page Draft Content 973198455 to Takeuchi et al 2007a

2021-02-03T17:53:23Z

Scipediacontent moved page Draft Content 973198455 to Takeuchi et al 2007a

Scipediacontent: Created page with " == Abstract == This paper proposes a low power VLIW processor generation method by automatically extracting non-redundant activation conditions of pipeline registers for clo..."

2021-02-03T17:53:19Z

Created page with " == Abstract == This paper proposes a low power VLIW processor generation method by automatically extracting non-redundant activation conditions of pipeline registers for clo..."

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== Abstract ==

This paper proposes a low power VLIW processor generation method by automatically extracting non-redundant activation conditions of pipeline registers for clock gating. It is important for the best power reduction by clock gating to create control signals that can completely shut off redundant clock supplies for registers. In order to generate the control signals automatically, the proposed method utilizes high-level architecture information called Micro-Operation Descriptions, which describes a VLIW processor architecture. Exploiting the Micro-Operation Descriptions in a VLIW processor generation process, the proposed method automatically extracts the non-redundant activation conditions that can control clock gating to supply the minimum clocks to the pipeline registers. Using the non-redundant activation condition extraction, the proposed method achieves short calculation time and low area overhead; the proposed method can be applied to VLIW processor generation. Experimental results show that the VLIW processor generated with proposed method achieves power reduction about 60% compared to the non-clock-gated VLIW processor, and about 35% compared to the VLIW processor that is applied clock gating by PowerCompiler with negligible area overhead.

== Original document ==

The different versions of the original document can be found in:

* [http://www.cecs.uci.edu/~papers/esweek07/codes/p227.pdf http://www.cecs.uci.edu/~papers/esweek07/codes/p227.pdf]

* [http://www.cecs.uci.edu/~papers/esweek07/codes/p227.pdf http://www.cecs.uci.edu/~papers/esweek07/codes/p227.pdf],
: [https://dblp.uni-trier.de/db/conf/codes/codes2007.html#IwatoSTI07 https://dblp.uni-trier.de/db/conf/codes/codes2007.html#IwatoSTI07],
: [http://yadda.icm.edu.pl/yadda/element/bwmeta1.element.ieee-000005753846 http://yadda.icm.edu.pl/yadda/element/bwmeta1.element.ieee-000005753846],
: [https://dl.acm.org/citation.cfm?doid=1289816.1289872 https://dl.acm.org/citation.cfm?doid=1289816.1289872],
: [https://academic.microsoft.com/#/detail/2105493068 https://academic.microsoft.com/#/detail/2105493068]

* [http://dl.acm.org/ft_gateway.cfm?id=1289872&ftid=452886&dwn=1 http://dl.acm.org/ft_gateway.cfm?id=1289872&ftid=452886&dwn=1],
: [http://dx.doi.org/10.1145/1289816.1289872 http://dx.doi.org/10.1145/1289816.1289872]

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Takeuchi et al 2007a - Revision history

Scipediacontent: Scipediacontent moved page Draft Content 973198455 to Takeuchi et al 2007a

Scipediacontent: Created page with " == Abstract == This paper proposes a low power VLIW processor generation method by automatically extracting non-redundant activation conditions of pipeline registers for clo..."