Sun et al 2011b - Revision history

Scipediacontent at 08:34, 6 March 2021

2021-03-06T08:34:42Z

Scipediacontent: Scipediacontent moved page Draft Content 723135796 to Sun et al 2011b

2021-02-08T09:11:06Z

Scipediacontent moved page Draft Content 723135796 to Sun et al 2011b

Scipediacontent: Created page with " == Abstract == 1.2V 10bit 83MS/s pipeline ADC implemented in 130nm CMOS Technology is described with practical design techniques and considerations. Emphasis was placed on..."

2021-02-08T09:11:03Z

Created page with " == Abstract == 1.2V 10bit 83MS/s pipeline ADC implemented in 130nm CMOS Technology is described with practical design techniques and considerations. Emphasis was placed on..."

New page

== Abstract ==

1.2V 10bit 83MS/s pipeline ADC implemented in 130nm CMOS Technology is described with practical design techniques and considerations. Emphasis was placed on noise analysis and capacitance optimization, which helps to reduce both die area and power consumption. Design experiences of operational amplifier, comparator and switches were also shared. This design achieves INL and DNL of +0.65/-0.53LSB and +0.33/-0.33LSB respectively, while SNDR is 57.7dB.

== Original document ==

The different versions of the original document can be found in:

* [http://juuli.fi/Record/0247838612 http://juuli.fi/Record/0247838612]

* [http://juuli.fi/Record/0252995111 http://juuli.fi/Record/0252995111]

* [http://xplorestaging.ieee.org/ielx5/5752641/5754186/05754276.pdf?arnumber=5754276 http://xplorestaging.ieee.org/ielx5/5752641/5754186/05754276.pdf?arnumber=5754276],
: [http://dx.doi.org/10.1109/uksim.2011.107 http://dx.doi.org/10.1109/uksim.2011.107]

* [http://yadda.icm.edu.pl/yadda/element/bwmeta1.element.ieee-000005754276 http://yadda.icm.edu.pl/yadda/element/bwmeta1.element.ieee-000005754276],
: [https://dblp.uni-trier.de/db/conf/uksim/uksim2011.html#SunMP11 https://dblp.uni-trier.de/db/conf/uksim/uksim2011.html#SunMP11],
: [http://ieeexplore.ieee.org/document/5754276 http://ieeexplore.ieee.org/document/5754276],
: [http://doi.org/10.1109/UKSIM.2011.107 http://doi.org/10.1109/UKSIM.2011.107],
: [https://doi.org/10.1109/UKSIM.2011.107 https://doi.org/10.1109/UKSIM.2011.107],
: [https://dl.acm.org/citation.cfm?id=1978173 https://dl.acm.org/citation.cfm?id=1978173],
: [https://ieeexplore.ieee.org/document/5754276 https://ieeexplore.ieee.org/document/5754276],
: [https://academic.microsoft.com/#/detail/2115291449 https://academic.microsoft.com/#/detail/2115291449]

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 == Abstract ==
 .2V 10bit 83MS/s pipeline ADC implemented in 130nm CMOS Technology is described with practical design techniques and considerations. Emphasis was placed on noise analysis and capacitance optimization, which helps to reduce both die area and power consumption. Design experiences of operational amplifier, comparator and switches were also shared. This design achieves INL and DNL of +0.65/-0.53LSB and +0.33/-0.33LSB respectively, while SNDR is 57.7dB.
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 == Original document ==

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