Scipediacontent: Scipediacontent moved page Draft Content 279615220 to Ruiz-Amaya et al 2011a

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Scipediacontent moved page Draft Content 279615220 to Ruiz-Amaya et al 2011a

Scipediacontent: Created page with " == Abstract == novel transistor-level synthesis procedure for pipeline ADCs is presented. This procedure is able to directly map high-level converter specifications onto tr..."

2021-02-16T09:31:44Z

Created page with " == Abstract == novel transistor-level synthesis procedure for pipeline ADCs is presented. This procedure is able to directly map high-level converter specifications onto tr..."

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== Abstract ==

novel transistor-level synthesis procedure for pipeline ADCs is presented. This procedure is able to directly map high-level converter specifications onto transistor sizes and biasing conditions. It is based on the combination of behavioral models for performance evaluation, optimization routines to minimize the power and area consumption of the circuit solution, and an algorithm to efficiently constraint the converter design space. This algorithm precludes the cost of lengthy bottom-up verifications and speeds up the synthesis task. The approach is herein demonstrated via the design of a 0.13 ¿m CMOS 10 bits@60 MS/s pipeline ADC with energy consumption per conversion of only 0.54 pJ@1 MHz, making it one of the most energy-efficient 10-bit video-rate pipeline ADCs reported to date. The computational cost of this design is of only 25 min of CPU time, and includes the evaluation of 13 different pipeline architectures potentially feasible for the targeted specifications. The optimum design derived from the synthesis procedure has been fine tuned to support PVT variations, laid out together with other auxiliary blocks, and fabricated. The experimental results show a power consumption of 23 mW@1.2 V and an effective resolution of 9.47-bit@1 MHz. Bearing in mind that no specific power reduction strategy has been applied; the mentioned results confirm the reliability of the proposed approach.

Peer Reviewed

== Original document ==

The different versions of the original document can be found in:

* [http://hdl.handle.net/10261/83360 http://hdl.handle.net/10261/83360]

* [http://xplorestaging.ieee.org/ielx5/8919/6085808/05944995.pdf?arnumber=5944995 http://xplorestaging.ieee.org/ielx5/8919/6085808/05944995.pdf?arnumber=5944995],
: [http://dx.doi.org/10.1109/tcsi.2011.2157746 http://dx.doi.org/10.1109/tcsi.2011.2157746]

* [https://ieeexplore.ieee.org/document/5944995 https://ieeexplore.ieee.org/document/5944995],
: [https://digital.csic.es/handle/10261/83360 https://digital.csic.es/handle/10261/83360],
: [http://yadda.icm.edu.pl/yadda/element/bwmeta1.element.ieee-000005944995 http://yadda.icm.edu.pl/yadda/element/bwmeta1.element.ieee-000005944995],
: [https://dblp.uni-trier.de/db/journals/tcas/tcasI58.html#Ruiz-AmayaDR11 https://dblp.uni-trier.de/db/journals/tcas/tcasI58.html#Ruiz-AmayaDR11],
: [https://idus.us.es/handle/11441/90825 https://idus.us.es/handle/11441/90825],
: [https://academic.microsoft.com/#/detail/2127201524 https://academic.microsoft.com/#/detail/2127201524]

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Ruiz-Amaya et al 2011a - Revision history

Scipediacontent: Scipediacontent moved page Draft Content 279615220 to Ruiz-Amaya et al 2011a

Scipediacontent: Created page with " == Abstract == novel transistor-level synthesis procedure for pipeline ADCs is presented. This procedure is able to directly map high-level converter specifications onto tr..."