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		<title>Pillonnet et al 2017a - Revision history</title>
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		<updated>2026-05-30T12:28:42Z</updated>
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		<id>https://www.scipedia.com/wd/index.php?title=Pillonnet_et_al_2017a&amp;diff=198448&amp;oldid=prev</id>
		<title>Scipediacontent: Scipediacontent moved page Draft Content 620195831 to Pillonnet et al 2017a</title>
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				<updated>2021-02-01T21:47:46Z</updated>
		
		<summary type="html">&lt;p&gt;Scipediacontent moved page &lt;a href=&quot;/public/Draft_Content_620195831&quot; class=&quot;mw-redirect&quot; title=&quot;Draft Content 620195831&quot;&gt;Draft Content 620195831&lt;/a&gt; to &lt;a href=&quot;/public/Pillonnet_et_al_2017a&quot; title=&quot;Pillonnet et al 2017a&quot;&gt;Pillonnet et al 2017a&lt;/a&gt;&lt;/p&gt;
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				&lt;td colspan='1' style=&quot;background-color: white; color:black; text-align: center;&quot;&gt;← Older revision&lt;/td&gt;
				&lt;td colspan='1' style=&quot;background-color: white; color:black; text-align: center;&quot;&gt;Revision as of 21:47, 1 February 2021&lt;/td&gt;
				&lt;/tr&gt;&lt;tr&gt;&lt;td colspan='2' style='text-align: center;' lang='en'&gt;&lt;div class=&quot;mw-diff-empty&quot;&gt;(No difference)&lt;/div&gt;
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		<author><name>Scipediacontent</name></author>	</entry>

	<entry>
		<id>https://www.scipedia.com/wd/index.php?title=Pillonnet_et_al_2017a&amp;diff=198447&amp;oldid=prev</id>
		<title>Scipediacontent: Created page with &quot; == Abstract ==  International audience; Adiabatic logic is an alternative architecture design style to reduce the power consumption of digital cores by using AC power supply...&quot;</title>
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				<updated>2021-02-01T21:47:42Z</updated>
		
		<summary type="html">&lt;p&gt;Created page with &amp;quot; == Abstract ==  International audience; Adiabatic logic is an alternative architecture design style to reduce the power consumption of digital cores by using AC power supply...&amp;quot;&lt;/p&gt;
&lt;p&gt;&lt;b&gt;New page&lt;/b&gt;&lt;/p&gt;&lt;div&gt;&lt;br /&gt;
== Abstract ==&lt;br /&gt;
&lt;br /&gt;
International audience; Adiabatic logic is an alternative architecture design style to reduce the power consumption of digital cores by using AC power supply instead of DC ones. The energy saving of the digital gates is strongly related to the efficiency of adiabatic AC power supplies. In this paper, we propose a resonant reversible power-clock supply design with four different phases. The resonance deviation between the four power-clock supplies is synchronized thanks to 12 control signals (3 controls signals per power-clock supply). We derive the energy dissipation of a 4-stage PFAL pipeline circuit supplied with the proposed resonant powerclock supply, which can dissipate up to 2.9 times less energy than a non-adiabatic CMOS pipeline.&lt;br /&gt;
&lt;br /&gt;
&lt;br /&gt;
== Original document ==&lt;br /&gt;
&lt;br /&gt;
The different versions of the original document can be found in:&lt;br /&gt;
&lt;br /&gt;
* [https://hal-lirmm.ccsd.cnrs.fr/lirmm-01768831 https://hal-lirmm.ccsd.cnrs.fr/lirmm-01768831]&lt;br /&gt;
&lt;br /&gt;
* [http://xplorestaging.ieee.org/ielx7/8121842/8123622/08123661.pdf?arnumber=8123661 http://xplorestaging.ieee.org/ielx7/8121842/8123622/08123661.pdf?arnumber=8123661],&lt;br /&gt;
: [http://dx.doi.org/10.1109/icrc.2017.8123661 http://dx.doi.org/10.1109/icrc.2017.8123661]&lt;br /&gt;
&lt;br /&gt;
* [https://hal-lirmm.ccsd.cnrs.fr/lirmm-01768831 https://hal-lirmm.ccsd.cnrs.fr/lirmm-01768831],&lt;br /&gt;
: [https://dblp.uni-trier.de/db/conf/icrc/icrc2017.html#JeanniotPNAT17 https://dblp.uni-trier.de/db/conf/icrc/icrc2017.html#JeanniotPNAT17],&lt;br /&gt;
: [https://academic.microsoft.com/#/detail/2775246436 https://academic.microsoft.com/#/detail/2775246436]&lt;/div&gt;</summary>
		<author><name>Scipediacontent</name></author>	</entry>

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