Perais Seznec 2013a - Revision history

Scipediacontent at 17:26, 25 January 2021

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Scipediacontent at 10:43, 22 January 2021

2021-01-22T10:43:37Z

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2020-10-26T14:45:01Z

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Scipediacontent: Created page with " == Abstract == A fait l'objet d'une publication Ã "High Performance Computer Architecture (HPCA) 2014" Lien : http://people.irisa.fr/Arthur.Perais/data/HPCA%2714_Practica..."

2020-10-26T14:44:58Z

Created page with " == Abstract == A fait l'objet d'une publication Ã "High Performance Computer Architecture (HPCA) 2014" Lien : http://people.irisa.fr/Arthur.Perais/data/HPCA%2714_Practica..."

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== Abstract ==

A fait l'objet d'une publication Ã "High Performance Computer Architecture (HPCA) 2014" Lien : http://people.irisa.fr/Arthur.Perais/data/HPCA%2714_Practical_VP.pdf; Dedicating more silicon area to single thread performance will necessarily be considered as worthwhile in future - potentially heterogeneous - multicores. In particular, Value prediction (VP) was proposed in the mid 90's to enhance the performance of high-end uniprocessors by breaking true data dependencies. In this paper, we reconsider the concept of Value Prediction in the contemporary context and show its potential as a direction to improve current single thread performance. First, building on top of research carried out during the previous decade on confidence estimation, we show that every value predictor is amenable to very high prediction accuracy using very simple hardware. This clears the path to an implementation of VP without a complex selective reissue mechanism to absorb mispredictions, where prediction is performed in the in-order pipeline frond-end and validation is performed in the in-order pipeline back-end, while the out-of-order engine is only marginally modified. Second, when predicting back-to-back occurrences of the same instruction, previous context-based value predictors relying on local value history exhibit a complex critical loop that should ideally be implemented in a single cycle. To bypass this requirement, we introduce a new value predictor VTAGE harnessing the global branch history. VTAGE can seamlessly predict back-to-back occurrences, allowing predictions to span over several cycles. It achieves higher performance than previously proposed context-based predictors. Specifically, using SPEC'00 and SPEC'06 benchmarks, our simulations show that combining VTAGE and a Stride-based predictor yields up to 65% speedup on a fairly aggressive pipeline without support for selective reissue.; DÃ©dier plus de surface de silicium Ã la performance sÃ©quentielle sera nÃ©cessairement considÃ©rÃ© comme digne d'interÃªt dans un futur proche. En particulier, la PrÃ©diction de Valeurs (VP) a Ã©tÃ© proposÃ©e dans les annÃ©es 90 afin d'amÃ©liorer la performance sÃ©quentielle des processeurs haute-performance en cassant les dÃ©pendances de donnÃ©es entre instructions. Dans ce papier, nous revisitons le concept de PrÃ©diction de Valeurs dans un contexte contemporain et montrons son potentiel d'amÃ©lioration de la performance sÃ©quentielle. SpÃ©cifiquement, utilisant les suites de benchmarks SPEC'00 et SPEC'06, nos simulations montrent qu'en combinant notre prÃ©dicteur, VTAGE, avec un prÃ©dicteur de type Stride, des gains de performances allant jusqu'Ã 65% peuvent Ãªtre observÃ©s sur un pipeline relativement agressif mais sans rÃ©-exÃ©cution sÃ©lective en cas de mauvaise prÃ©diction.

Document type: External research report

== Original document ==

The different versions of the original document can be found in:

* [https://hal.inria.fr/hal-01088116/file/practical_VP.pdf https://hal.inria.fr/hal-01088116/file/practical_VP.pdf]

* [http://hal.inria.fr/hal-00904743 http://hal.inria.fr/hal-00904743],[http://hal.inria.fr/docs/00/90/47/43/PDF/RR-8395.pdf http://hal.inria.fr/docs/00/90/47/43/PDF/RR-8395.pdf]

* [http://xplorestaging.ieee.org/ielx7/6823235/6835920/06835952.pdf?arnumber=6835952 http://xplorestaging.ieee.org/ielx7/6823235/6835920/06835952.pdf?arnumber=6835952],[http://dx.doi.org/10.1109/hpca.2014.6835952 http://dx.doi.org/10.1109/hpca.2014.6835952]

* [https://hal.inria.fr/hal-00904743 https://hal.inria.fr/hal-00904743],[https://hal.inria.fr/hal-00904743/document https://hal.inria.fr/hal-00904743/document],[https://hal.inria.fr/hal-00904743/file/RR-8395.pdf https://hal.inria.fr/hal-00904743/file/RR-8395.pdf]

* [https://hal.inria.fr/hal-00904743 https://hal.inria.fr/hal-00904743],[https://hal.inria.fr/hal-00904743/document https://hal.inria.fr/hal-00904743/document]

* [https://hal.inria.fr/hal-01088116 https://hal.inria.fr/hal-01088116],[https://hal.inria.fr/hal-01088116/document https://hal.inria.fr/hal-01088116/document],[https://hal.inria.fr/hal-01088116/file/practical_VP.pdf https://hal.inria.fr/hal-01088116/file/practical_VP.pdf]

* [https://hal.inria.fr/hal-01088116/document https://hal.inria.fr/hal-01088116/document],[https://hal.inria.fr/hal-01088116 https://hal.inria.fr/hal-01088116],[http://ieeexplore.ieee.org/abstract/document/6835952 http://ieeexplore.ieee.org/abstract/document/6835952],[https://academic.microsoft.com/#/detail/2053496002 https://academic.microsoft.com/#/detail/2053496002]

← Older revision		Revision as of 17:26, 25 January 2021
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	== Abstract ==		== Abstract ==

−	A fait l'objet d'une publication Ã "High Performance Computer Architecture (HPCA) 2014" Lien : http://people.irisa.fr/Arthur.Perais/data/HPCA%2714_Practical_VP.pdf; Dedicating more silicon area to single thread performance will necessarily be considered as worthwhile in future - potentially heterogeneous - multicores. In particular, Value prediction (VP) was proposed in the mid 90's to enhance the performance of high-end uniprocessors by breaking true data dependencies. In this paper, we reconsider the concept of Value Prediction in the contemporary context and show its potential as a direction to improve current single thread performance. First, building on top of research carried out during the previous decade on confidence estimation, we show that every value predictor is amenable to very high prediction accuracy using very simple hardware. This clears the path to an implementation of VP without a complex selective reissue mechanism to absorb mispredictions, where prediction is performed in the in-order pipeline frond-end and validation is performed in the in-order pipeline back-end, while the out-of-order engine is only marginally modified. Second, when predicting back-to-back occurrences of the same instruction, previous context-based value predictors relying on local value history exhibit a complex critical loop that should ideally be implemented in a single cycle. To bypass this requirement, we introduce a new value predictor VTAGE harnessing the global branch history. VTAGE can seamlessly predict back-to-back occurrences, allowing predictions to span over several cycles. It achieves higher performance than previously proposed context-based predictors. Specifically, using SPEC'00 and SPEC'06 benchmarks, our simulations show that combining VTAGE and a Stride-based predictor yields up to 65% speedup on a fairly aggressive pipeline without support for selective reissue.; ~~DÃ©dier~~ plus de surface de silicium Ã la performance ~~sÃ©quentielle~~ sera ~~nÃ©cessairement considÃ©rÃ©~~ comme digne d'~~interÃªt~~ dans un futur proche. En particulier, la ~~PrÃ©diction~~ de Valeurs (VP) a ~~Ã©tÃ© proposÃ©e~~ dans les ~~annÃ©es~~ 90 afin d'~~amÃ©liorer~~ la performance ~~sÃ©quentielle~~ des processeurs haute-performance en cassant les ~~dÃ©pendances~~ de ~~donnÃ©es~~ entre instructions. Dans ce papier, nous revisitons le concept de ~~PrÃ©diction~~ de Valeurs dans un contexte contemporain et montrons son potentiel d'~~amÃ©lioration~~ de la performance ~~sÃ©quentielle~~. ~~SpÃ©cifiquement~~, utilisant les suites de benchmarks SPEC'00 et SPEC'06, nos simulations montrent qu'en combinant notre ~~prÃ©dicteur~~, VTAGE, avec un ~~prÃ©dicteur~~ de type Stride, des gains de performances allant jusqu'Ã 65% peuvent ~~Ãªtre observÃ©s~~ sur un pipeline relativement agressif mais sans ~~rÃ©~~-~~exÃ©cution sÃ©lective~~ en cas de mauvaise ~~prÃ©diction~~.	+	fait l'objet d'une publication à "High Performance Computer Architecture (HPCA) 2014" Lien : http://people.irisa.fr/Arthur.Perais/data/HPCA%2714_Practical_VP.pdf; Dedicating more silicon area to single thread performance will necessarily be considered as worthwhile in future - potentially heterogeneous - multicores. In particular, Value prediction (VP) was proposed in the mid 90's to enhance the performance of high-end uniprocessors by breaking true data dependencies. In this paper, we reconsider the concept of Value Prediction in the contemporary context and show its potential as a direction to improve current single thread performance. First, building on top of research carried out during the previous decade on confidence estimation, we show that every value predictor is amenable to very high prediction accuracy using very simple hardware. This clears the path to an implementation of VP without a complex selective reissue mechanism to absorb mispredictions, where prediction is performed in the in-order pipeline frond-end and validation is performed in the in-order pipeline back-end, while the out-of-order engine is only marginally modified. Second, when predicting back-to-back occurrences of the same instruction, previous context-based value predictors relying on local value history exhibit a complex critical loop that should ideally be implemented in a single cycle. To bypass this requirement, we introduce a new value predictor VTAGE harnessing the global branch history. VTAGE can seamlessly predict back-to-back occurrences, allowing predictions to span over several cycles. It achieves higher performance than previously proposed context-based predictors. Specifically, using SPEC'00 and SPEC'06 benchmarks, our simulations show that combining VTAGE and a Stride-based predictor yields up to 65% speedup on a fairly aggressive pipeline without support for selective reissue.; Dédier plus de surface de silicium à la performance séquentielle sera nécessairement considéré comme digne d'interêt dans un futur proche. En particulier, la Prédiction de Valeurs (VP) a été proposée dans les années 90 afin d'améliorer la performance séquentielle des processeurs haute-performance en cassant les dépendances de données entre instructions. Dans ce papier, nous revisitons le concept de Prédiction de Valeurs dans un contexte contemporain et montrons son potentiel d'amélioration de la performance séquentielle. Spécifiquement, utilisant les suites de benchmarks SPEC'00 et SPEC'06, nos simulations montrent qu'en combinant notre prédicteur, VTAGE, avec un prédicteur de type Stride, des gains de performances allant jusqu'à 65% peuvent être observés sur un pipeline relativement agressif mais sans ré-exécution sélective en cas de mauvaise prédiction.

@@ Line 3: / Line 3: @@
 A fait l'objet d'une publication Ã  "High Performance Computer Architecture (HPCA) 2014" Lien : http://people.irisa.fr/Arthur.Perais/data/HPCA%2714_Practical_VP.pdf; Dedicating more silicon area to single thread performance will necessarily be considered as worthwhile in future - potentially heterogeneous - multicores. In particular, Value prediction (VP) was proposed in the mid 90's to enhance the performance of high-end uniprocessors by breaking true data dependencies. In this paper, we reconsider the concept of Value Prediction in the contemporary context and show its potential as a direction to improve current single thread performance. First, building on top of research carried out during the previous decade on confidence estimation, we show that every value predictor is amenable to very high prediction accuracy using very simple hardware. This clears the path to an implementation of VP without a complex selective reissue mechanism to absorb mispredictions, where prediction is performed in the in-order pipeline frond-end and validation is performed in the in-order pipeline back-end, while the out-of-order engine is only marginally modified. Second, when predicting back-to-back occurrences of the same instruction, previous context-based value predictors relying on local value history exhibit a complex critical loop that should ideally be implemented in a single cycle. To bypass this requirement, we introduce a new value predictor VTAGE harnessing the global branch history. VTAGE can seamlessly predict back-to-back occurrences, allowing predictions to span over several cycles. It achieves higher performance than previously proposed context-based predictors. Specifically, using SPEC'00 and SPEC'06 benchmarks, our simulations show that combining VTAGE and a Stride-based predictor yields up to 65% speedup on a fairly aggressive pipeline without support for selective reissue.; DÃ©dier plus de surface de silicium Ã  la performance sÃ©quentielle sera nÃ©cessairement considÃ©rÃ© comme digne d'interÃªt dans un futur proche. En particulier, la PrÃ©diction de Valeurs (VP) a Ã©tÃ© proposÃ©e dans les annÃ©es 90 afin d'amÃ©liorer la performance sÃ©quentielle des processeurs haute-performance en cassant les dÃ©pendances de donnÃ©es entre instructions. Dans ce papier, nous revisitons le concept de PrÃ©diction de Valeurs dans un contexte contemporain et montrons son potentiel d'amÃ©lioration de la performance sÃ©quentielle. SpÃ©cifiquement, utilisant les suites de benchmarks SPEC'00 et SPEC'06, nos simulations montrent qu'en combinant notre prÃ©dicteur, VTAGE, avec un prÃ©dicteur de type Stride, des gains de performances allant jusqu'Ã  65% peuvent Ãªtre observÃ©s sur un pipeline relativement agressif mais sans rÃ©-exÃ©cution sÃ©lective en cas de mauvaise prÃ©diction.
@@ Line 13: / Line 11: @@
 * [https://hal.inria.fr/hal-01088116/file/practical_VP.pdf https://hal.inria.fr/hal-01088116/file/practical_VP.pdf]
-* [http://hal.inria.fr/hal-00904743 http://hal.inria.fr/hal-00904743],[http://hal.inria.fr/docs/00/90/47/43/PDF/RR-8395.pdf http://hal.inria.fr/docs/00/90/47/43/PDF/RR-8395.pdf]
+* [http://xplorestaging.ieee.org/ielx7/6823235/6835920/06835952.pdf?arnumber=6835952 http://xplorestaging.ieee.org/ielx7/6823235/6835920/06835952.pdf?arnumber=6835952],
+: [http://dx.doi.org/10.1109/hpca.2014.6835952 http://dx.doi.org/10.1109/hpca.2014.6835952]
-* [http://xplorestaging.ieee.org/ielx7/6823235/6835920/06835952.pdf?arnumber=6835952 http://xplorestaging.ieee.org/ielx7/6823235/6835920/06835952.pdf?arnumber=6835952],[http://dx.doi.org/10.1109/hpca.2014.6835952 http://dx.doi.org/10.1109/hpca.2014.6835952]
-−
-* [https://hal.inria.fr/hal-00904743 https://hal.inria.fr/hal-00904743],[https://hal.inria.fr/hal-00904743/document https://hal.inria.fr/hal-00904743/document],[https://hal.inria.fr/hal-00904743/file/RR-8395.pdf https://hal.inria.fr/hal-00904743/file/RR-8395.pdf]
-* [https://hal.inria.fr/hal-00904743 https://hal.inria.fr/hal-00904743],[https://hal.inria.fr/hal-00904743/document https://hal.inria.fr/hal-00904743/document]
+* [https://hal.inria.fr/hal-00904743 https://hal.inria.fr/hal-00904743],
-* [https://hal.inria.fr/hal-01088116 https://hal.inria.fr/hal-01088116],[https://hal.inria.fr/hal-01088116/document https://hal.inria.fr/hal-01088116/document],[https://hal.inria.fr/hal-01088116/file/practical_VP.pdf https://hal.inria.fr/hal-01088116/file/practical_VP.pdf]
+* [https://hal.inria.fr/hal-01088116 https://hal.inria.fr/hal-01088116],
-* [https://hal.inria.fr/hal-01088116/document https://hal.inria.fr/hal-01088116/document],[https://hal.inria.fr/hal-01088116 https://hal.inria.fr/hal-01088116],[http://ieeexplore.ieee.org/abstract/document/6835952 http://ieeexplore.ieee.org/abstract/document/6835952],[https://academic.microsoft.com/#/detail/2053496002 https://academic.microsoft.com/#/detail/2053496002]
+* [https://hal.inria.fr/hal-01088116/document https://hal.inria.fr/hal-01088116/document],

← Older revision	Revision as of 14:45, 26 October 2020
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