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== Abstract ==<br />
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IEEE International Symposium on Circuits and Systems, pp. 2258 – 2261, Seattle, EUA A low-power 1.2 V 6-bit 1-GS/s time-interleaved pipeline ADC designed in 130 nm CMOS is described. It is based on a new 2-channel 1.5-bit MDAC that performs openloop residue amplification using a shared amplifier employing local-feedback. Time mismatches between channels are highly attenuated, simply by using two passive front-end Sample-and-Hold circuits, with dedicated switch-linearization control circuits, driven by a single clock phase. Simulated results of the ADC achieve 5.35-bit ENOB, with 20 mW and without requiring any gain control/calibration scheme.<br />
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== Original document ==<br />
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The different versions of the original document can be found in:<br />
<br />
* [http://hdl.handle.net/10362/4037 http://hdl.handle.net/10362/4037]<br />
<br />
* [https://run.unl.pt/bitstream/10362/4037/1/Goes_2008.pdf https://run.unl.pt/bitstream/10362/4037/1/Goes_2008.pdf]<br />
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* [http://xplorestaging.ieee.org/ielx5/4534149/4541329/04541903.pdf?arnumber=4541903 http://xplorestaging.ieee.org/ielx5/4534149/4541329/04541903.pdf?arnumber=4541903],<br />
: [http://dx.doi.org/10.1109/iscas.2008.4541903 http://dx.doi.org/10.1109/iscas.2008.4541903]<br />
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* [https://dblp.uni-trier.de/db/conf/iscas/iscas2008.html#GalhardoGP08 https://dblp.uni-trier.de/db/conf/iscas/iscas2008.html#GalhardoGP08],<br />
: [https://run.unl.pt/bitstream/10362/4037/1/Goes_2008.pdf https://run.unl.pt/bitstream/10362/4037/1/Goes_2008.pdf],<br />
: [http://yadda.icm.edu.pl/yadda/element/bwmeta1.element.ieee-000004541903 http://yadda.icm.edu.pl/yadda/element/bwmeta1.element.ieee-000004541903],<br />
: [http://ieeexplore.ieee.org/document/4541903 http://ieeexplore.ieee.org/document/4541903],<br />
: [https://run.unl.pt/handle/10362/4037 https://run.unl.pt/handle/10362/4037],<br />
: [https://academic.microsoft.com/#/detail/2125293613 https://academic.microsoft.com/#/detail/2125293613]</div>Scipediacontent