Scipediacontent: Scipediacontent moved page Draft Content 573289625 to Muramatsu Narumi 2019a

2021-01-28T20:01:33Z

Scipediacontent moved page Draft Content 573289625 to Muramatsu Narumi 2019a

Scipediacontent: Created page with " == Abstract == In the era of the IoT (Internet of Things) and Edge computing, SoC (System on Chip) with an FPGA (Field Programmable Gate Array) is a suitable solution for em..."

2021-01-28T20:01:27Z

Created page with " == Abstract == In the era of the IoT (Internet of Things) and Edge computing, SoC (System on Chip) with an FPGA (Field Programmable Gate Array) is a suitable solution for em..."

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== Abstract ==

In the era of the IoT (Internet of Things) and Edge computing, SoC (System on Chip) with an FPGA (Field Programmable Gate Array) is a suitable solution for embedded systems because it supports running rich operating systems on general-purpose CPUs, as well as the FPGA’s acceleration for specific computing. One problem of designing an accelerator on an FPGA is that optimization of the logic for the accelerator is not automatic and much trial and error is needed before attaining peak performance from the SoC. In this paper we propose a method to reduce the development time of the accelerator using N-body simulation as a target application. Based on the hardware resources needed for several pipelines of the accelerator and their performance estimation model, we can estimate how many pipelines can be implemented on an SoC. In addition, the amount of memory each pipeline requires for attaining maximum performance is suggested. Our model agreed with the actual calculation speed for different constraining conditions.

== Original document ==

The different versions of the original document can be found in:

* [http://dx.doi.org/10.5220/0008066500650074 http://dx.doi.org/10.5220/0008066500650074]

* [https://doi.org/10.5220/0008066500650074 https://doi.org/10.5220/0008066500650074] under the license cc-by-nc-nd

* [https://dblp.uni-trier.de/db/conf/peccs/peccs2019.html#NarumiM19 https://dblp.uni-trier.de/db/conf/peccs/peccs2019.html#NarumiM19],
: [https://academic.microsoft.com/#/detail/2978904333 https://academic.microsoft.com/#/detail/2978904333]

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Muramatsu Narumi 2019a - Revision history

Scipediacontent: Scipediacontent moved page Draft Content 573289625 to Muramatsu Narumi 2019a

Scipediacontent: Created page with " == Abstract == In the era of the IoT (Internet of Things) and Edge computing, SoC (System on Chip) with an FPGA (Field Programmable Gate Array) is a suitable solution for em..."