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		<title>Minkovich Cong 2009a - Revision history</title>
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		<updated>2026-04-18T17:19:52Z</updated>
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	<entry>
		<id>https://www.scipedia.com/wd/index.php?title=Minkovich_Cong_2009a&amp;diff=202311&amp;oldid=prev</id>
		<title>Scipediacontent: Scipediacontent moved page Draft Content 431407218 to Minkovich Cong 2009a</title>
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				<updated>2021-02-02T05:35:12Z</updated>
		
		<summary type="html">&lt;p&gt;Scipediacontent moved page &lt;a href=&quot;/public/Draft_Content_431407218&quot; class=&quot;mw-redirect&quot; title=&quot;Draft Content 431407218&quot;&gt;Draft Content 431407218&lt;/a&gt; to &lt;a href=&quot;/public/Minkovich_Cong_2009a&quot; title=&quot;Minkovich Cong 2009a&quot;&gt;Minkovich Cong 2009a&lt;/a&gt;&lt;/p&gt;
&lt;table class=&quot;diff diff-contentalign-left&quot; data-mw=&quot;interface&quot;&gt;
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				&lt;td colspan='1' style=&quot;background-color: white; color:black; text-align: center;&quot;&gt;← Older revision&lt;/td&gt;
				&lt;td colspan='1' style=&quot;background-color: white; color:black; text-align: center;&quot;&gt;Revision as of 05:35, 2 February 2021&lt;/td&gt;
				&lt;/tr&gt;&lt;tr&gt;&lt;td colspan='2' style='text-align: center;' lang='en'&gt;&lt;div class=&quot;mw-diff-empty&quot;&gt;(No difference)&lt;/div&gt;
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		<author><name>Scipediacontent</name></author>	</entry>

	<entry>
		<id>https://www.scipedia.com/wd/index.php?title=Minkovich_Cong_2009a&amp;diff=202310&amp;oldid=prev</id>
		<title>Scipediacontent: Created page with &quot; == Abstract ==  In this paper we present a novel metric for measuring and optimizing the performance of circuits that operate with the clock period smaller than the worst-cas...&quot;</title>
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				<updated>2021-02-02T05:35:06Z</updated>
		
		<summary type="html">&lt;p&gt;Created page with &amp;quot; == Abstract ==  In this paper we present a novel metric for measuring and optimizing the performance of circuits that operate with the clock period smaller than the worst-cas...&amp;quot;&lt;/p&gt;
&lt;p&gt;&lt;b&gt;New page&lt;/b&gt;&lt;/p&gt;&lt;div&gt;&lt;br /&gt;
== Abstract ==&lt;br /&gt;
&lt;br /&gt;
In this paper we present a novel metric for measuring and optimizing the performance of circuits that operate with the clock period smaller than the worst-case delay. In particular, we developed an efficient logic optimization operation “balance” and a library mapping algorithm named BTWLibMap. Together they are able to reduce the probability of a timing error by 2.3X while only incurring a 4% area overhead.&lt;br /&gt;
&lt;br /&gt;
&lt;br /&gt;
== Original document ==&lt;br /&gt;
&lt;br /&gt;
The different versions of the original document can be found in:&lt;br /&gt;
&lt;br /&gt;
* [http://ballade.cs.ucla.edu/~cong/papers/vlsi-dat_final_v5.pdf http://ballade.cs.ucla.edu/~cong/papers/vlsi-dat_final_v5.pdf]&lt;br /&gt;
&lt;br /&gt;
* [http://cadlab.cs.ucla.edu/%7Econg/papers/vlsi-dat_final_v5.pdf http://cadlab.cs.ucla.edu/%7Econg/papers/vlsi-dat_final_v5.pdf],&lt;br /&gt;
: [http://yadda.icm.edu.pl/yadda/element/bwmeta1.element.ieee-000005158121 http://yadda.icm.edu.pl/yadda/element/bwmeta1.element.ieee-000005158121],&lt;br /&gt;
: [https://academic.microsoft.com/#/detail/2134165615 https://academic.microsoft.com/#/detail/2134165615]&lt;br /&gt;
&lt;br /&gt;
* [http://xplorestaging.ieee.org/ielx5/5128899/5158074/05158121.pdf?arnumber=5158121 http://xplorestaging.ieee.org/ielx5/5128899/5158074/05158121.pdf?arnumber=5158121],&lt;br /&gt;
: [http://dx.doi.org/10.1109/vdat.2009.5158121 http://dx.doi.org/10.1109/vdat.2009.5158121]&lt;/div&gt;</summary>
		<author><name>Scipediacontent</name></author>	</entry>

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