Scipediacontent: Scipediacontent moved page Draft Content 339890163 to Kirner et al 2006a

2021-01-28T19:52:42Z

Scipediacontent moved page Draft Content 339890163 to Kirner et al 2006a

Scipediacontent: Created page with " == Abstract == The counter-intuitive timing behavior of certain features in superscalar processors that cause severe problems for existing worst-case execution time analysis..."

2021-01-28T19:52:37Z

Created page with " == Abstract == The counter-intuitive timing behavior of certain features in superscalar processors that cause severe problems for existing worst-case execution time analysis..."

New page

== Abstract ==

The counter-intuitive timing behavior of certain features in superscalar processors that cause severe problems for existing worst-case execution time analysis (WCET) methods is called timing anomalies. In this paper, we identify structural sources potentially causing timing anomalies in superscalar pipelines. We provide examples for cases where timing anomalies can arise in much simpler hardware architectures than commonly supposed (i.e., even in hardware containing only in-orderfunctional units). We elaborate the general principle behind timing anomalies and propose a general criterion (resource allocation criterion) that provides a necessary (but not sufficient) condition for the occurrence of timing anomalies in a processor. This principle allows to state the absence of timing anomalies for a specific combination of hardware and software and thus forms a solid theoretic foundation for the time-predictable execution of real-time software on complex processor hardware.

== Original document ==

The different versions of the original document can be found in:

* [http://uhra.herts.ac.uk/bitstream/2299/6333/1/905626.pdf http://uhra.herts.ac.uk/bitstream/2299/6333/1/905626.pdf]

* [http://xplorestaging.ieee.org/ielx5/10545/33358/01579148.pdf?arnumber=1579148 http://xplorestaging.ieee.org/ielx5/10545/33358/01579148.pdf?arnumber=1579148],
: [http://dx.doi.org/10.1109/qsic.2005.49 http://dx.doi.org/10.1109/qsic.2005.49]

* [https://dblp.uni-trier.de/db/conf/qsic/qsic2005.html#WenzelKPR05 https://dblp.uni-trier.de/db/conf/qsic/qsic2005.html#WenzelKPR05],
: [https://uhra.herts.ac.uk/handle/2299/6333 https://uhra.herts.ac.uk/handle/2299/6333],
: [https://ieeexplore.ieee.org/document/1579148 https://ieeexplore.ieee.org/document/1579148],
: [http://ieeexplore.ieee.org/document/1579148 http://ieeexplore.ieee.org/document/1579148],
: [http://uhra.herts.ac.uk/bitstream/handle/2299/6333/905626.pdf?sequence=1 http://uhra.herts.ac.uk/bitstream/handle/2299/6333/905626.pdf?sequence=1],
: [https://academic.microsoft.com/#/detail/2112533211 https://academic.microsoft.com/#/detail/2112533211]

← Older revision	Revision as of 19:52, 28 January 2021
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Kirner et al 2006a - Revision history

Scipediacontent: Scipediacontent moved page Draft Content 339890163 to Kirner et al 2006a

Scipediacontent: Created page with " == Abstract == The counter-intuitive timing behavior of certain features in superscalar processors that cause severe problems for existing worst-case execution time analysis..."