Scipediacontent: Scipediacontent moved page Draft Content 681799899 to Hoe Nguyen 2018a

2021-01-28T16:01:14Z

Scipediacontent moved page Draft Content 681799899 to Hoe Nguyen 2018a

Scipediacontent: Created page with " == Abstract == This paper presents an FPGA runtime framework that demonstrates the feasibility of using dynamic partial reconfiguration (DPR) for time-sharing an FPGA by mul..."

2021-01-28T16:01:09Z

Created page with " == Abstract == This paper presents an FPGA runtime framework that demonstrates the feasibility of using dynamic partial reconfiguration (DPR) for time-sharing an FPGA by mul..."

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== Abstract ==

This paper presents an FPGA runtime framework that demonstrates the feasibility of using dynamic partial reconfiguration (DPR) for time-sharing an FPGA by multiple realtime computer vision pipelines. The presented time-sharing runtime framework manages an FPGA fabric that can be round-robin time-shared by different pipelines at the time scale of individual frames. In this new use-case, the challenge is to achieve useful performance despite high reconfiguration time. The paper describes the basic runtime support as well as four optimizations necessary to achieve realtime performance given the limitations of DPR on today's FPGAs. The paper provides a characterization of a working runtime framework prototype on a Xilinx ZC706 development board. The paper also reports the performance of realtime computer vision pipelines when time-shared.

== Original document ==

The different versions of the original document can be found in:

* [http://arxiv.org/abs/1805.10431 http://arxiv.org/abs/1805.10431]

* [http://arxiv.org/pdf/1805.10431 http://arxiv.org/pdf/1805.10431]

* [http://xplorestaging.ieee.org/ielx7/8529150/8530786/08533499.pdf?arnumber=8533499 http://xplorestaging.ieee.org/ielx7/8529150/8530786/08533499.pdf?arnumber=8533499],
: [http://dx.doi.org/10.1109/fpl.2018.00046 http://dx.doi.org/10.1109/fpl.2018.00046]

* [https://dblp.uni-trier.de/db/conf/fpl/fpl2018.html#NguyenH18 https://dblp.uni-trier.de/db/conf/fpl/fpl2018.html#NguyenH18],
: [https://academic.microsoft.com/#/detail/2963292517 https://academic.microsoft.com/#/detail/2963292517]

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Hoe Nguyen 2018a - Revision history

Scipediacontent: Scipediacontent moved page Draft Content 681799899 to Hoe Nguyen 2018a

Scipediacontent: Created page with " == Abstract == This paper presents an FPGA runtime framework that demonstrates the feasibility of using dynamic partial reconfiguration (DPR) for time-sharing an FPGA by mul..."