Scipediacontent: Scipediacontent moved page Draft Content 737582398 to Goes et al 2008b

2021-02-03T15:27:02Z

Scipediacontent moved page Draft Content 737582398 to Goes et al 2008b

Scipediacontent: Created page with " == Abstract == IEEE International Symposium on Circuits and Systems, pp. 220 – 223, Seattle, EUA This paper presents a 14-bit 1.5 MSample/s two-stage algorithmic ADC with..."

2021-02-03T15:26:59Z

Created page with " == Abstract == IEEE International Symposium on Circuits and Systems, pp. 220 – 223, Seattle, EUA This paper presents a 14-bit 1.5 MSample/s two-stage algorithmic ADC with..."

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== Abstract ==

IEEE International Symposium on Circuits and Systems, pp. 220 – 223, Seattle, EUA This paper presents a 14-bit 1.5 MSample/s two-stage algorithmic ADC with a power-and-area efficiency better than 0.5 pJmm2 per conversion. This competes with the most efficient architectures available today namely, ΣΔ and self-calibrated pipeline. The 2 stages of the ADC are based on a new 1.5-bit mismatch-insensitive MDAC and simulations demonstrate that a THD of –79 dB and an ENOB better than 12 bits can be reached without self-calibration.

== Original document ==

The different versions of the original document can be found in:

* [http://hdl.handle.net/10362/4062 http://hdl.handle.net/10362/4062]

* [https://run.unl.pt/bitstream/10362/4062/1/Goes_2008.pdf https://run.unl.pt/bitstream/10362/4062/1/Goes_2008.pdf]

* [http://xplorestaging.ieee.org/ielx5/4534149/4541329/04541394.pdf?arnumber=4541394 http://xplorestaging.ieee.org/ielx5/4534149/4541329/04541394.pdf?arnumber=4541394],
: [http://dx.doi.org/10.1109/iscas.2008.4541394 http://dx.doi.org/10.1109/iscas.2008.4541394]

* [https://dblp.uni-trier.de/db/conf/iscas/iscas2008.html#EsperancaGTGPS08 https://dblp.uni-trier.de/db/conf/iscas/iscas2008.html#EsperancaGTGPS08],
: [http://yadda.icm.edu.pl/yadda/element/bwmeta1.element.ieee-000004541394 http://yadda.icm.edu.pl/yadda/element/bwmeta1.element.ieee-000004541394],
: [https://run.unl.pt/bitstream/10362/4062/1/Goes_2008.pdf https://run.unl.pt/bitstream/10362/4062/1/Goes_2008.pdf],
: [https://ieeexplore.ieee.org/xpl/articleDetails.jsp?reload=true&arnumber=4541394 https://ieeexplore.ieee.org/xpl/articleDetails.jsp?reload=true&arnumber=4541394],
: [https://run.unl.pt/handle/10362/4062 https://run.unl.pt/handle/10362/4062],
: [https://academic.microsoft.com/#/detail/2132322377 https://academic.microsoft.com/#/detail/2132322377]

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Goes et al 2008b - Revision history

Scipediacontent: Scipediacontent moved page Draft Content 737582398 to Goes et al 2008b

Scipediacontent: Created page with " == Abstract == IEEE International Symposium on Circuits and Systems, pp. 220 – 223, Seattle, EUA This paper presents a 14-bit 1.5 MSample/s two-stage algorithmic ADC with..."