Gibbard et al 1977a - Revision history

Scipediacontent at 16:13, 25 January 2021

2021-01-25T16:13:35Z

Scipediacontent at 10:26, 22 January 2021

2021-01-22T10:26:35Z

Scipediacontent: Scipediacontent moved page Draft Content 663930810 to Gibbard et al 1977a

2020-10-26T08:58:10Z

Scipediacontent moved page Draft Content 663930810 to Gibbard et al 1977a

Scipediacontent: Created page with " == Abstract == A study was made of the flow of data and the simultaneous processing needed to reduce the 10/sup 7/ to 10/sup 8/ triggers per second expected at ISABELLE to a..."

2020-10-26T08:58:08Z

Created page with " == Abstract == A study was made of the flow of data and the simultaneous processing needed to reduce the 10/sup 7/ to 10/sup 8/ triggers per second expected at ISABELLE to a..."

New page

== Abstract ==

A study was made of the flow of data and the simultaneous processing needed to reduce the 10/sup 7/ to 10/sup 8/ triggers per second expected at ISABELLE to a number of events on the order of 10 to 100 per second which would be written on magnetic tape. It was assumed that within 100 ns of the event a fast pretrigger would have reduced the data rate to at most 10/sup 7/ per second. At that point, data from all sense elements in the experiment would be fed into a 1-..mu..s-long pipeline. Within the first 1 ..mu..s (while the data are in the first pipeline) another level of triggering would reduce the trigger rate to at most 10/sup 6/ per second. The data would then be fed into a second pipeline which is 50 ..mu..s long. During the 50 ..mu..s the data are in the second pipeline, a more sophisticated level of triggering (slow trigger) would reduce the trigger rate to a level that can be handled by standard data processing techniques (microprocessors or larger machines), i.e., 10/sup 2/ to 10/sup 3/ per second. The pipelines and the buffer between them, a sequential address memory, are described first, andmoreÂ Â» then several alternative schemes for the pretrigger and slow trigger are presented. 10 figures.Â«Â le

Document type: Report

== Full document ==
<pdf>Media:Draft_Content_663930810-beopen88-9211-document.pdf</pdf>

== Original document ==

The different versions of the original document can be found in:

* [http://dx.doi.org/10.2172/6167080 http://dx.doi.org/10.2172/6167080]

* [https://digital.library.unt.edu/ark:/67531/metadc1110201/m2/1/high_res_d/6167080.pdf https://digital.library.unt.edu/ark:/67531/metadc1110201/m2/1/high_res_d/6167080.pdf]

* [http://www.osti.gov/servlets/purl/6167080-2F2YcT http://www.osti.gov/servlets/purl/6167080-2F2YcT],[https://academic.microsoft.com/#/detail/62102482 https://academic.microsoft.com/#/detail/62102482]

← Older revision		Revision as of 16:13, 25 January 2021
Line 2:		Line 2:
	== Abstract ==		== Abstract ==

−	A study was made of the flow of data and the simultaneous processing needed to reduce the 10/sup 7/ to 10/sup 8/ triggers per second expected at ISABELLE to a number of events on the order of 10 to 100 per second which would be written on magnetic tape. It was assumed that within 100 ns of the event a fast pretrigger would have reduced the data rate to at most 10/sup 7/ per second. At that point, data from all sense elements in the experiment would be fed into a 1-..mu..s-long pipeline. Within the first 1 ..mu..s (while the data are in the first pipeline) another level of triggering would reduce the trigger rate to at most 10/sup 6/ per second. The data would then be fed into a second pipeline which is 50 ..mu..s long. During the 50 ..mu..s the data are in the second pipeline, a more sophisticated level of triggering (slow trigger) would reduce the trigger rate to a level that can be handled by standard data processing techniques (microprocessors or larger machines), i.e., 10/sup 2/ to 10/sup 3/ per second. The pipelines and the buffer between them, a sequential address memory, are described first, ~~andmoreÂ Â»~~ then several alternative schemes for the pretrigger and slow trigger are presented. 10 figures.~~Â«Â le~~	+	study was made of the flow of data and the simultaneous processing needed to reduce the 10/sup 7/ to 10/sup 8/ triggers per second expected at ISABELLE to a number of events on the order of 10 to 100 per second which would be written on magnetic tape. It was assumed that within 100 ns of the event a fast pretrigger would have reduced the data rate to at most 10/sup 7/ per second. At that point, data from all sense elements in the experiment would be fed into a 1-..mu..s-long pipeline. Within the first 1 ..mu..s (while the data are in the first pipeline) another level of triggering would reduce the trigger rate to at most 10/sup 6/ per second. The data would then be fed into a second pipeline which is 50 ..mu..s long. During the 50 ..mu..s the data are in the second pipeline, a more sophisticated level of triggering (slow trigger) would reduce the trigger rate to a level that can be handled by standard data processing techniques (microprocessors or larger machines), i.e., 10/sup 2/ to 10/sup 3/ per second. The pipelines and the buffer between them, a sequential address memory, are described first, andmore » then several alternative schemes for the pretrigger and slow trigger are presented. 10 figures.« le

@@ Line 3: / Line 3: @@
 A study was made of the flow of data and the simultaneous processing needed to reduce the 10/sup 7/ to 10/sup 8/ triggers per second expected at ISABELLE to a number of events on the order of 10 to 100 per second which would be written on magnetic tape. It was assumed that within 100 ns of the event a fast pretrigger would have reduced the data rate to at most 10/sup 7/ per second. At that point, data from all sense elements in the experiment would be fed into a 1-..mu..s-long pipeline. Within the first 1 ..mu..s (while the data are in the first pipeline) another level of triggering would reduce the trigger rate to at most 10/sup 6/ per second. The data would then be fed into a second pipeline which is 50 ..mu..s long. During the 50 ..mu..s the data are in the second pipeline, a more sophisticated level of triggering (slow trigger) would reduce the trigger rate to a level that can be handled by standard data processing techniques (microprocessors or larger machines), i.e., 10/sup 2/ to 10/sup 3/ per second. The pipelines and the buffer between them, a sequential address memory, are described first, andmoreÂ Â» then several alternative schemes for the pretrigger and slow trigger are presented. 10 figures.Â«Â le
@@ Line 18: / Line 13: @@
 * [https://digital.library.unt.edu/ark:/67531/metadc1110201/m2/1/high_res_d/6167080.pdf https://digital.library.unt.edu/ark:/67531/metadc1110201/m2/1/high_res_d/6167080.pdf]
-* [http://www.osti.gov/servlets/purl/6167080-2F2YcT http://www.osti.gov/servlets/purl/6167080-2F2YcT],[https://academic.microsoft.com/#/detail/62102482 https://academic.microsoft.com/#/detail/62102482]
+* [http://www.osti.gov/servlets/purl/6167080-2F2YcT http://www.osti.gov/servlets/purl/6167080-2F2YcT],

← Older revision	Revision as of 08:58, 26 October 2020
(No difference)