Scipediacontent: Scipediacontent moved page Draft Content 309329517 to Finlayson et al 2015a

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Scipediacontent moved page Draft Content 309329517 to Finlayson et al 2015a

Scipediacontent: Created page with " == Abstract == Statically pipelined processors have a fully exposed datapath where all portions of the pipeline are directly controlled by effects within an instruction, whi..."

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Created page with " == Abstract == Statically pipelined processors have a fully exposed datapath where all portions of the pipeline are directly controlled by effects within an instruction, whi..."

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== Abstract ==

Statically pipelined processors have a fully exposed datapath where all portions of the pipeline are directly controlled by effects within an instruction, which simplifies hardware and enables a new level of compiler optimizations. This paper describes an effect scheduling strategy to aggressively compact instructions, which has a critical impact on code size and performance. Unique scheduling challenges include more frequent name dependences and fewer renaming opportunities due to static pipeline (SP) registers being dedicated for specific operations. We also realized the SP in a hardware implementation language (VHDL) to evaluate the real energy benefits. Despite the compiler challenges, we achieve performance, code size, and energy improvements compared to a conventional MIPS processor.

== Original document ==

The different versions of the original document can be found in:

* [http://www.cs.fsu.edu/%7Ewhalley/papers/cases15.pdf http://www.cs.fsu.edu/%7Ewhalley/papers/cases15.pdf]

* [http://www.cs.fsu.edu/~whalley/papers/cases15.pdf http://www.cs.fsu.edu/~whalley/papers/cases15.pdf],
: [https://scholarworks.boisestate.edu/cs_facpubs/62 https://scholarworks.boisestate.edu/cs_facpubs/62],
: [http://www.diva-portal.org/smash/record.jsf?pid=diva2:847507 http://www.diva-portal.org/smash/record.jsf?pid=diva2:847507],
: [https://dblp.uni-trier.de/db/conf/cases/cases2015.html#DavisBGSFRCUWT15 https://dblp.uni-trier.de/db/conf/cases/cases2015.html#DavisBGSFRCUWT15],
: [http://sjalander.com/research/pdf/sjalander-cases2015.pdf http://sjalander.com/research/pdf/sjalander-cases2015.pdf],
: [https://works.bepress.com/gang-ryung_uh/17 https://works.bepress.com/gang-ryung_uh/17],
: [http://uu.diva-portal.org/smash/record.jsf?pid=diva2:847507 http://uu.diva-portal.org/smash/record.jsf?pid=diva2:847507],
: [https://academic.microsoft.com/#/detail/2038404002 https://academic.microsoft.com/#/detail/2038404002]

* [http://xplorestaging.ieee.org/ielx7/7313573/7324531/07324557.pdf?arnumber=7324557 http://xplorestaging.ieee.org/ielx7/7313573/7324531/07324557.pdf?arnumber=7324557],
: [http://dx.doi.org/10.1109/cases.2015.7324557 http://dx.doi.org/10.1109/cases.2015.7324557]

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Finlayson et al 2015a - Revision history

Scipediacontent: Scipediacontent moved page Draft Content 309329517 to Finlayson et al 2015a

Scipediacontent: Created page with " == Abstract == Statically pipelined processors have a fully exposed datapath where all portions of the pipeline are directly controlled by effects within an instruction, whi..."