Scipediacontent: Scipediacontent moved page Draft Content 837678125 to Dwiel et al 2015a

2021-02-02T04:04:14Z

Scipediacontent moved page Draft Content 837678125 to Dwiel et al 2015a

Scipediacontent: Created page with " == Abstract == FabScalar is a recently published tool for automatically generating superscalar cores, of different pipeline widths, depths and sizes. The output of FabScalar..."

2021-02-02T04:04:06Z

Created page with " == Abstract == FabScalar is a recently published tool for automatically generating superscalar cores, of different pipeline widths, depths and sizes. The output of FabScalar..."

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== Abstract ==

FabScalar is a recently published tool for automatically generating superscalar cores, of different pipeline widths, depths and sizes. The output of FabScalar is a synthesizable register-transfer-level (RTL) description of the desired core. While this capability makes sophisticated cores more accessible to designers and researchers, meaningful applications require reducing RTL descriptions to physical designs. This paper presents the first systematic physical design study of FabScalar-generated superscalar cores.

== Original document ==

The different versions of the original document can be found in:

* [http://dx.doi.org/10.1109/vlsi-soc.2012.6379024 http://dx.doi.org/10.1109/vlsi-soc.2012.6379024]

* [http://people.engr.ncsu.edu/ericro/publications/conference_VLSI-SoC-2012.pdf http://people.engr.ncsu.edu/ericro/publications/conference_VLSI-SoC-2012.pdf]

* [http://xplorestaging.ieee.org/ielx7/7332057/7332058/07332095.pdf?arnumber=7332095 http://xplorestaging.ieee.org/ielx7/7332057/7332058/07332095.pdf?arnumber=7332095],
: [http://dx.doi.org/10.1109/vlsi-soc.2012.7332095 http://dx.doi.org/10.1109/vlsi-soc.2012.7332095]

* [https://dblp.uni-trier.de/db/conf/vlsi/vlsisoc2012.html#ChoudharyDR12 https://dblp.uni-trier.de/db/conf/vlsi/vlsisoc2012.html#ChoudharyDR12],
: [https://people.engr.ncsu.edu/ericro/publications/conference_VLSI-SoC-2012.pdf https://people.engr.ncsu.edu/ericro/publications/conference_VLSI-SoC-2012.pdf],
: [http://yadda.icm.edu.pl/yadda/element/bwmeta1.element.ieee-000006379024 http://yadda.icm.edu.pl/yadda/element/bwmeta1.element.ieee-000006379024],
: [https://doi.org/10.1109/VLSI-SoC.2012.6379024 https://doi.org/10.1109/VLSI-SoC.2012.6379024],
: [https://academic.microsoft.com/#/detail/2164321609 https://academic.microsoft.com/#/detail/2164321609]

DOIS: 10.1109/vlsi-soc.2012.6379024 10.1109/vlsi-soc.2012.7332095

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Dwiel et al 2015a - Revision history

Scipediacontent: Scipediacontent moved page Draft Content 837678125 to Dwiel et al 2015a

Scipediacontent: Created page with " == Abstract == FabScalar is a recently published tool for automatically generating superscalar cores, of different pipeline widths, depths and sizes. The output of FabScalar..."