https://www.scipedia.com/wd/index.php?action=history&feed=atom&title=Dilillo_et_al_2015aDilillo et al 2015a - Revision history2026-10-24T02:30:27ZRevision history for this page on the wikiMediaWiki 1.27.0-wmf.10https://www.scipedia.com/wd/index.php?title=Dilillo_et_al_2015a&diff=207885&oldid=prevScipediacontent: Scipediacontent moved page Draft Content 202828973 to Dilillo et al 2015a2021-02-03T19:18:39Z<p>Scipediacontent moved page <a href="/public/Draft_Content_202828973" class="mw-redirect" title="Draft Content 202828973">Draft Content 202828973</a> to <a href="/public/Dilillo_et_al_2015a" title="Dilillo et al 2015a">Dilillo et al 2015a</a></p>
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</td></tr></table>Scipediacontenthttps://www.scipedia.com/wd/index.php?title=Dilillo_et_al_2015a&diff=207884&oldid=prevScipediacontent: Created page with " == Abstract == International audience; Increasing vulnerability of transistors and interconnects due to CMOS technology scaling is continuously challenging the reliability o..."2021-02-03T19:18:36Z<p>Created page with " == Abstract == International audience; Increasing vulnerability of transistors and interconnects due to CMOS technology scaling is continuously challenging the reliability o..."</p>
<p><b>New page</b></p><div><br />
== Abstract ==<br />
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International audience; Increasing vulnerability of transistors and interconnects due to CMOS technology scaling is continuously challenging the reliability of future electronic circuits and systems. Lifetime reliability is gaining attention over performance as a design factor even for lower-end commodity applications. In this paper we propose an effective hybrid fault-tolerant architecture able to deal with permanent and transient faults in combinational parts of pipelined cores. The principle consists in triplicating the combinational logic parts but, unlike TMR, only two copies run in parallel while the third one remains in standby until an error is detected. We have implemented this approach on a MIPS microprocessor as case study. Experiments show that our approach is comparable to TMR in terms of area with a notable power saving and offers a full protection against transient and permanent faults.<br />
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== Original document ==<br />
<br />
The different versions of the original document can be found in:<br />
<br />
* [https://hal-lirmm.ccsd.cnrs.fr/lirmm-01272730 https://hal-lirmm.ccsd.cnrs.fr/lirmm-01272730]<br />
<br />
* [http://xplorestaging.ieee.org/ielx7/7127855/7138715/07138733.pdf?arnumber=7138733 http://xplorestaging.ieee.org/ielx7/7127855/7138715/07138733.pdf?arnumber=7138733],<br />
: [http://dx.doi.org/10.1109/ets.2015.7138733 http://dx.doi.org/10.1109/ets.2015.7138733]<br />
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* [https://hal-lirmm.ccsd.cnrs.fr/lirmm-01272730 https://hal-lirmm.ccsd.cnrs.fr/lirmm-01272730],<br />
: [https://dblp.uni-trier.de/db/conf/ets/ets2015.html#WaliVBDG15 https://dblp.uni-trier.de/db/conf/ets/ets2015.html#WaliVBDG15],<br />
: [https://ieeexplore.ieee.org/document/7138733 https://ieeexplore.ieee.org/document/7138733],<br />
: [https://academic.microsoft.com/#/detail/1493708942 https://academic.microsoft.com/#/detail/1493708942]</div>Scipediacontent