Scipediacontent: Scipediacontent moved page Draft Content 965883476 to Bhunia et al 2005a

2021-02-02T05:50:45Z

Scipediacontent moved page Draft Content 965883476 to Bhunia et al 2005a

Scipediacontent: Created page with " == Abstract == Operating frequency of a pipelined circuit is determined by the delay of the slowest pipeline stage. However, under statistical delay variation in sub-100nm t..."

2021-02-02T05:50:35Z

Created page with " == Abstract == Operating frequency of a pipelined circuit is determined by the delay of the slowest pipeline stage. However, under statistical delay variation in sub-100nm t..."

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== Abstract ==

Operating frequency of a pipelined circuit is determined by the delay of the slowest pipeline stage. However, under statistical delay variation in sub-100nm technology regime, the slowest stage is not readily identifiable and the estimation of the pipeline yield with respect to a target delay is a challenging problem. We have proposed analytical models to estimate yield for a pipelined design based on delay distributions of individual pipe stages. Using the proposed models, we have shown that change in logic depth and imbalance between the stage delays can improve the yield of a pipeline. A statistical methodology has been developed to optimally design a pipeline circuit for enhancing yield. Optimization results show that, proper imbalance among the stage delays in a pipeline improves design yield by 9% for the same area and performance (and area reduction by about 8.4% under a yield constraint) over a balanced design.

Comment: Submitted on behalf of EDAA (http://www.edaa.com/)

== Original document ==

The different versions of the original document can be found in:

* [http://arxiv.org/abs/0710.4663 http://arxiv.org/abs/0710.4663]

* [http://arxiv.org/pdf/0710.4663 http://arxiv.org/pdf/0710.4663]

* [http://xplorestaging.ieee.org/ielx5/9609/30361/01395704.pdf?arnumber=1395704 http://xplorestaging.ieee.org/ielx5/9609/30361/01395704.pdf?arnumber=1395704],
: [http://dx.doi.org/10.1109/date.2005.278 http://dx.doi.org/10.1109/date.2005.278]

* [https://dblp.uni-trier.de/db/journals/corr/corr0710.html#abs-0710-4663 https://dblp.uni-trier.de/db/journals/corr/corr0710.html#abs-0710-4663],
: [https://arxiv.org/pdf/0710.4663 https://arxiv.org/pdf/0710.4663],
: [https://ui.adsabs.harvard.edu/abs/2007arXiv0710.4663D/abstract https://ui.adsabs.harvard.edu/abs/2007arXiv0710.4663D/abstract],
: [https://dl.acm.org/citation.cfm?id=1049246 https://dl.acm.org/citation.cfm?id=1049246],
: [https://arxiv.org/abs/0710.4663 https://arxiv.org/abs/0710.4663],
: [https://www.date-conference.com/proceedings-archive/PAPERS/2005/DATE05/PDFFILES/07G_1.PDF https://www.date-conference.com/proceedings-archive/PAPERS/2005/DATE05/PDFFILES/07G_1.PDF],
: [https://www.researchgate.net/profile/Animesh_Datta/publication/29647249_Statistical_Modeling_of_Pipeline_Delay_and_Design_of_Pipeline_under_Process_Variation_to_Enhance_Yield_in_sub-100nm_Technologies/links/0c96052a0ca205d509000000.pdf?disableCoverPage=true https://www.researchgate.net/profile/Animesh_Datta/publication/29647249_Statistical_Modeling_of_Pipeline_Delay_and_Design_of_Pipeline_under_Process_Variation_to_Enhance_Yield_in_sub-100nm_Technologies/links/0c96052a0ca205d509000000.pdf?disableCoverPage=true],
: [http://www.cecs.uci.edu/~papers/date05/papers/2005/date05/pdffiles/07g_1.pdf http://www.cecs.uci.edu/~papers/date05/papers/2005/date05/pdffiles/07g_1.pdf],
: [https://academic.microsoft.com/#/detail/2159874000 https://academic.microsoft.com/#/detail/2159874000]

* [https://hal.archives-ouvertes.fr/hal-00181238 https://hal.archives-ouvertes.fr/hal-00181238],
: [https://hal.archives-ouvertes.fr/hal-00181238/document https://hal.archives-ouvertes.fr/hal-00181238/document],
: [https://hal.archives-ouvertes.fr/hal-00181238/file/228820926.pdf https://hal.archives-ouvertes.fr/hal-00181238/file/228820926.pdf]

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Scipediacontent: Scipediacontent moved page Draft Content 965883476 to Bhunia et al 2005a

Scipediacontent: Created page with " == Abstract == Operating frequency of a pipelined circuit is determined by the delay of the slowest pipeline stage. However, under statistical delay variation in sub-100nm t..."