Scipediacontent: Scipediacontent moved page Draft Content 651923976 to Amano et al 2012a

2021-02-02T07:34:06Z

Scipediacontent moved page Draft Content 651923976 to Amano et al 2012a

Scipediacontent: Created page with " == Abstract == We propose a multi-voltage (multi-Vdd) variable pipeline router to reduce the power consumption of Network-on-Chips (NoCs) designed for chip multi-processors..."

2021-02-02T07:34:03Z

Created page with " == Abstract == We propose a multi-voltage (multi-Vdd) variable pipeline router to reduce the power consumption of Network-on-Chips (NoCs) designed for chip multi-processors..."

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== Abstract ==

We propose a multi-voltage (multi-Vdd) variable pipeline router to reduce the power consumption of Network-on-Chips (NoCs) designed for chip multi-processors (CMPs). Our multi-Vdd variable pipeline router adjusts its pipeline depth (i.e., communication latency) and supply voltage level in response to the applied workload. Unlike dynamic voltage and frequency scaling (DVFS) routers, the operating frequency is the same for all routers throughout the CMP; thus, there is no need to synchronize neighboring routers working at different frequencies. In this paper, we implemented the multi-Vdd variable pipeline router, which selects two supply voltage levels and pipeline modes, using a 65nm CMOS process and evaluated it using a full-system CMP simulator. Evaluation results show that although the application performance degraded by 1.0% to 2.1%, the standby power of NoCs reduced by 10.4% to 44.4%.

== Original document ==

The different versions of the original document can be found in:

* [http://www.arc.ics.keio.ac.jp/%7Ematutani/papers/matsutani_aspdac2012.pdf http://www.arc.ics.keio.ac.jp/%7Ematutani/papers/matsutani_aspdac2012.pdf]

* [http://www.arc.ics.keio.ac.jp/~matutani/papers/matsutani_aspdac2012.pdf http://www.arc.ics.keio.ac.jp/~matutani/papers/matsutani_aspdac2012.pdf],
: [http://yadda.icm.edu.pl/yadda/element/bwmeta1.element.ieee-000006164982 http://yadda.icm.edu.pl/yadda/element/bwmeta1.element.ieee-000006164982],
: [https://shibaura.pure.elsevier.com/en/publications/a-multi-vdd-dynamic-variable-pipeline-on-chip-router-for-cmps https://shibaura.pure.elsevier.com/en/publications/a-multi-vdd-dynamic-variable-pipeline-on-chip-router-for-cmps],
: [https://dblp.uni-trier.de/db/conf/aspdac/aspdac2012.html#MatsutaniHKUNA12 https://dblp.uni-trier.de/db/conf/aspdac/aspdac2012.html#MatsutaniHKUNA12],
: [https://keio.pure.elsevier.com/en/publications/a-multi-vdd-dynamic-variable-pipeline-on-chip-router-for-cmps https://keio.pure.elsevier.com/en/publications/a-multi-vdd-dynamic-variable-pipeline-on-chip-router-for-cmps],
: [https://ieeexplore.ieee.org/document/6164982 https://ieeexplore.ieee.org/document/6164982],
: [https://academic.microsoft.com/#/detail/2086936748 https://academic.microsoft.com/#/detail/2086936748]

* [http://xplorestaging.ieee.org/ielx5/6156603/6164924/06164982.pdf?arnumber=6164982 http://xplorestaging.ieee.org/ielx5/6156603/6164924/06164982.pdf?arnumber=6164982],
: [http://dx.doi.org/10.1109/aspdac.2012.6164982 http://dx.doi.org/10.1109/aspdac.2012.6164982]

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Amano et al 2012a - Revision history

Scipediacontent: Scipediacontent moved page Draft Content 651923976 to Amano et al 2012a

Scipediacontent: Created page with " == Abstract == We propose a multi-voltage (multi-Vdd) variable pipeline router to reduce the power consumption of Network-on-Chips (NoCs) designed for chip multi-processors..."