Abstract

Forensic analysis techniques, usually applied in criminal research, could also be used in libraries to access digital information stored in obsolete formats or storage devices. This article analyses some examples of forensic research departments created by libraries, and describes the minimal hardware and software elements required to set up a library unit specialized in forensic analysis. Two possible equipment settings are introduced and recommendations are given on how to organize a workflow to recover information stored in floppy disks, diskettes and old hard drives.

Abstract

Network operators have recently been developing multi-Gbps traffic monitoring tools that execute on commodity hardware and are part of the packet-processing pipelines realizing software dataplanes. These solutions allow sophisticated tasks to be performed on a per-packet basis, without relying on sampling or passive trace analysis, by leveraging the processing power available on servers. Although advances in packet capture have enabled intercepting packets from network cards at high rates, bottlenecks can still arise in the monitoring process as a result of concurrent access to shared processor resources, variations of the traffic skew, and unbalanced packet-rate spikes. In this paper we present an adaptive traffic monitoring approach that copes with emerging bottlenecks by timely detecting changes in the operational conditions and reconfiguring monitoring-related operations for subsets of traffic flows. Our solution performs responsive adaptations at the time scale of milliseconds and does not require a significant amount of resources. To demonstrate the capabilities of our approach we implemented it as part of a generic packet-processing pipeline and show that lossless traffic monitoring can be achieved for a wide range of conditions.

Abstract

© 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. Advanced Driver Assistance Systems (ADAS) and Autonomous Driving (AD) have drastically increased the performance demands of automotive systems. Suitable highperformance platforms building upon Graphic Processing Units (GPUs) have been developed to respond to this demand, being NVIDIA Jetson TX2 a relevant representative. However, whether high-performance GPU configurations are appropriate for automotive setups remains as an open question. This paper aims at providing light on this question by modelling an automotive GPU (Jetson TX2), analyzing its microarchitectural parameters against relevant benchmarks, and identifying specific configurations able to meaningfully increase performance within similar cost envelopes, or to decrease costs preserving original performance levels. Overall, our analysis opens the door to the optimization of automotive GPUs for further system efficiency. Peer Reviewed

Abstract

The present paper describes the framework and components of an instrumented vehicle for driver assistance and safety. The experimental platform is based on the use of an on-board computer vision system to capture the traffic signs, and on a multiple of electronic components to capture the vehicle state and identify drivers. The hardware architecture is designed with the purpose of making the deployment of functionalities related to driver assistance and road safety easy. The paper covers firstly the description of the hardware architecture, and then describes some of the implemented functionalities such as driver assistance based on traffic signs detection and recognition, traffic violation recorder, and a realization of an emergency call system. Manuscript received 15 February, 2012. This work was supported in part by the Regional Government of Madrid under the S2009/DPI-1509-SEGVAUTO grant, and the PN I+D+i under the TRA2010-20225-C03-02 SAMPLER grant.

Abstract

Conference of 10th IEEE International Symposium on Industrial Embedded Systems, SIES 2015 ; Conference Date: 8 June 2015 Through 10 June 2015; Conference Code:116797; International audience; Many-core architectures are promising hardware to design hard real-time systems as they are based on simpler and thus more predictable processors than multi-core systems. However, the worst-case behavior of the Network-on-Chip (NoC) for both inter-core and core to external memories or peripherals communications must be established. Several NoCs targeting hard real-time systems, made of specific hardware extensions, have been designed. However, none of these extensions are currently available in commercially existing NoC-based many-core architectures, that instead rely on wormhole switching with round-robin arbitration. In this paper, we thus demonstrate three properties of such NoC-based wormhole networks to identify worst-case scenarios and reduce the pessimism when modeling flows in contentions. We then describe and evaluate an algorithm to compute Worst-Case Traversal Time (WCTT) of flows that uses these properties. In particular, our results show that the pessimism can be reduced up to 50% compared to current state-of-the-art real-time packet schedulability analysis.