Abstract

Concept of fractional order calculus is as old as the regular calculus. With the advent of high speed and cost effective computing power, now it is possible to model the real world control and signal processing problems using fractional order calculus. For the past two decades, applications of fractional order calculus, in system modeling, control and signal processing, have grown rapidly. This paper presents a systematic procedure for hardware implementation of the basic operators of fractional calculus i.e. fractional integrator and derivative, using Grünwald–Letnikov definition, on field programmable gate array (FPGA) in LabVIEW environment. The simulation and hardware implementation results for fractional order integrator and derivative of sinusoid and square waveform signals for some selected fractional orders have been presented. A close agreement between the simulated and the experimental results demonstrated the suitability of FPGA device in fractional order control and signal processing applications. LabVIEW being one of the finest tools for measurement and control, and signal processing applications the fractional order operator implementation is expected to further enhance the capability of the tool to cater to the needs of advanced experimental research employing fractional order operators.

Abstract

The aim of this work is to design and code an embedded system for a portable automatic weather station. The portable station includes high performance sensors to measure parameters such as: i) wind speed and direction, micro perturbations and wind gusts, ii) air temperature, iii) solar radiation, iv) relative humidity, and v) atmospheric pressure. The main contribution of this work is the development of an embedded control system operating in real time. This system is based on a Field Programmable Gate Array (FPGA) device. The method developed guarantees high-resolution data acquisition of a number of samples in real time. The samples obtained are grouped and stored in a database, which will be used as a starting point for further analysis.

Abstract

International audience; Modern embedded processors have gone through multiple internal optimization to speed-up the average execution time e.g., caches, pipelines, branch prediction. Besides, internal communication mechanisms and shared resources like caches or buses have a significant impact on Worst-Case Execution Times (WCETs). Having an accurate estimate of a WCET is now a challenge. Probabilistic approaches provide a viable alternative to single WCET estimation. They consider WCET as a probabilistic distribution associated to uncertainty or risk.In this paper, we present synthetic benchmarks and associated analysis for several LEON3 configurations on FPGA targets. Benchmarking exposes key parameters to execution time variability allowing for accurate probabilistic modeling of system dynamics. We analyze the impact of architecture-level configurations on average and worst-case behaviors.; Les processeurs embarqués modernes sont passés par optimisation interne multiple pour accélérer l'exécution moyenne par exemple le temps, les caches, les pipelines, la prédiction de branchement. Par ailleurs, mécanismes de communication et de partage des ressources comme des caches ou bus ont un impact significatif sur le temps d'exécution pire des cas (WCETs). Avoir une estimation précise d'un WCET est maintenant en défi. Les approches probabilistes fournies pour des alternatives viables à Singles WCET estimation. Ils considèrent comme un WCET probabiliste la distribution associée à l'incertitude ou le risque du pire cas.Dans cet article, nous présentons des benchmarks synthétiques et associés analyse pour plusieurs configurations LEON3 sur FPGA cibles. Benchmarking expose l'effet de certains paramètres sur la variabilité de l'exécution des taches afin de permettre à la modélisation probabiliste précise de la dynamique du système. Nous analysons l'impact des configurations sur les comportements moyens et pire cas du systeme.

Abstract

International audience; Understanding the composition of the Internet traffic has many applications nowadays, mainly tracking bandwidth consuming applications, QoS-based traffic engineering and lawful interception of illegal traffic. Although many classification methods such as Support Vector Machines (SVM) have demonstrated their accuracy, not enough attention has been paid to the practical implementation of lightweight classifiers. In this paper, we consider the design of a real-time SVM classifier at many Gbps to allow online detection of categories of applications. Our solution is based on the design of a hardware accelerated SVM classifier on a FPGA board.

Abstract

"jats:p"This paper presents reconfigurable hardware architecture for smart road traffic system based on Field Programmable Gate Array (FPGA). The design can be reconfigured for different timing of the traffic signals according to the received and collected data read by the different sensors on the road; the design has been described using VHDL (VHSIC Hardware Description Language). The SRTM (Smart Road Traffic Management) System has some more features that help passenger to avoid traffic jamming by sending the collected information through web/mobile applications to find the best road between the start and destination points, which will be displayed on Google maps, at the same time it will also shows the points of traffic jamming on Google maps. SRTM system can also manage emergency vehicles such as ambulance and fire fighter and also can send snapshots and video streaming for different roads and junctions to show the points of traffic jamming. The design has been simulated and tested using ModelSim PE student edition 10.4. Spartan 3 FPGA starter kit from Xilinx has been used for implementing and testing the design in a hardware level. Document type: Article