Abstract

Submitted on behalf of EDAA (http://www.edaa.com/); International audience; The wider and wider use of high-performance processors as part of real-time systems makes it more and more difficult to guarantee that programs will respect their strict deadlines. While the computation of Worst-Case Execution Times relies on static analysis of the code, the challenge is to model with enough safety and accuracy the behaviour of intrisically dynamic components. In this paper, we focus on the dynamic branch predictor. Several models to bound the number of branch mispredictions have been previously published. Some of them exhibit a high complexity while other ones have shown that taking into account semantic information from the source code makes things more tractable. We extend this work to more general nested loop structures. We also give some simulation results that show that the way branch mispredictions are usually taken into account cannot be both safe and accurate in the case of high-performance pipelines. We propose a more realistic approach to be used as part of WCET computation.

Abstract

International audience; This SIG focuses on the engineering of automation in interactive critical systems. Automation has already been studied in a number of (sub-) disciplines and application fields: design, human factors, psychology, (software) engineering, aviation, health care, games. One distinguishing feature of the area we are focusing on is that in the field of interactive critical systems properties such as reliability, dependability, fault-tolerance are as important as usability, user experience or overall acceptance issues. The SIG targets at two problem areas: first the engineering of the user interaction with (partly-) autonomous systems: how to design, build and assess autonomous behavior, especially in cases where there is a need to represent on the user interface both autonomous and interactive objects. An example of such integration is the representation of an unmanned aerial vehicle (UAV) (where no direct interaction is possible), together with aircrafts (that have to be instructed by an air traffic controller to avoid the UAV). Second the design and engineering of user interaction in general for autonomous objects/systems (for example a cruise control in a car or an autopilot in an aircraft).

Abstract

National audience; This research paper proposes IEEE802.3az incorporated green algorithmic schemes on the software defined networking-based segment routing (SDN-based SR) centralized network. The proposed schemes are the green (i.e. the EAGER and CARE metrics) SDN-based SR networks with and without traffic engineering (TE) tunneling. Green metrics extend the IEEE 802.3az energy saving to the whole network, while tunneling avoids the load sharing mechanism included in the segment routing that is not convenient for energy saving purpose. The findings of emulation revealed that the energy efficiency under the EAGER-tunneling strategy is comparable to the conventional metric with TE tunneling, and the saving realized under the CARE-tunneling scheme is twofold in comparison with the LEGACY-tunneling strategy. Meanwhile, the energy saving performance achieved with all three metrics under TE non-tunneling was inferior to those with tunneling. Nonetheless, the lower end-to-end delay and lower maximum link utilization (MLU) were achievable with the non-tunneling strategy.

Abstract

International audience; The xMAS micro-architecture modeling language has been introduced by Intel to facilitate the formal representation and analysis of on-chip interconnect fabrics. In this paper, we introduce xMAStime, a new domain-specific language inspired by xMAS. xMAStime allows the modeling of full micro-architectures comprising certain classes of CPU pipelines, caches, and RAM. Given an in-order pipeline model in xMAStime, we automatically generate both a Cycle-Accurate, Bit-Accurate (CABA) hardware simulator and a timed instruction set simulator where time is accounted with safe upper bounds, as in the pipeline analysis step of Worst-Case Execution Time (WCET) analysis. The approach relies on the theory of endochronous systems, which allows us to ensure functional equivalence and timing consistency between the two generated simulators, using a delay-insensitivity argument. xMAStime is implemented over Lucid Synchrone-a dataflow synchronous language featuring a higher order type system and type inference, which facilitate the definition of our DSL. We use the new DSL to model and synthesize simulation code for a full-fledged MIPS32-based architecture.

Abstract

The emerging concept of SoC-AMS leads to research new top-down methodologies to aid systems designers in sizing analog and mixed devices. This work applies this idea to the high-level optimization of pipeline ADC. Considering a given technology, it consists in comparing different configurations according to their imperfections and their architectures without FFT computation or time-consuming simulations. The final selection is based on a figure of merit. Comment: Submitted on behalf of EDAA (http://www.edaa.com/)

Abstract

International audience; Modeling the execution of a processor and its instructions is a challenging problem, in particular in the presence of long pipelines, parallelism, and out-of-order execution. A naive approach based on finite state automata inevitably leads to an explosion in the number of states and is thus only applicable to simple minimalistic processors. During their execution, instructions may only proceed forward through the processor's datapath towards the end of the pipeline. The state of later pipeline stages is thus independent of potential hazards in preceding stages. This also applies for data hazards, i.e., we may observe data by-passing from a later stage to an earlier one, but not in the other direction. Based on this observation, we explore the use of a series of parallel finite automata to model the execution states of the processor's resources individually. The automaton model captures state updates of the individual resources along with the movement of instructions through the pipeline. A highly-flexible synchronization scheme built into the automata enables an elegant modeling of parallel computations, pipelining, and even out-of-order execution. An interesting property of our approach is the ability to model a subset of a given processor using a sub-automaton of the full execution model.

Abstract

International audience; The VHDL hardware description language is commonly used to describe Finite State Machine(FSM) models to be implemented on Field Programmable Gate Array(FPGA) devices. However, its versatility permits to describe behaviors that deviate from a true FSM leading to systems that are complex to prove, to document and to maintain. The purpose of this work is to propose a language and the associated tools to create FSMs through a dedicated and intuitive textual description. This language is inspired by the dot language used in Graphviz, a tool to define graphs, and adds all the necessary elements required to describe complex FSM models (using for instance memorized or non memorized actions and actions on states or transitions). Moreover some additional elements are proposed to enrich the standard FSM model such as the genericity that permits to define simultaneously multiple states, transitions or actions using a generative description. A multi-platform open source JAVA program named FSMPro-cess [1] is introduced. Based on the ANTLR parser generator, it achieves the automatic generation of all the required .vhdl files (component, package, instantiation example and testbench) and a .dot file that is used to generate an always up-to-date graphical representation of the model (hence its documentation). This tool also supports simple model checking and integration of additional VHDL code. It can be used conjointly with version control systems and is coupled with the open source GHDL simulator to allow fast prototyping. It can be used either with its Graphical User Interface either as a command line compiler for integration in makefiles.

Abstract

Operating frequency of a pipelined circuit is determined by the delay of the slowest pipeline stage. However, under statistical delay variation in sub-100nm technology regime, the slowest stage is not readily identifiable and the estimation of the pipeline yield with respect to a target delay is a challenging problem. We have proposed analytical models to estimate yield for a pipelined design based on delay distributions of individual pipe stages. Using the proposed models, we have shown that change in logic depth and imbalance between the stage delays can improve the yield of a pipeline. A statistical methodology has been developed to optimally design a pipeline circuit for enhancing yield. Optimization results show that, proper imbalance among the stage delays in a pipeline improves design yield by 9% for the same area and performance (and area reduction by about 8.4% under a yield constraint) over a balanced design. Comment: Submitted on behalf of EDAA (http://www.edaa.com/)

Abstract

Detailed modeling of processors and high performance cycle-accurate simulators are essential for today's hardware and software design. These problems are challenging enough by themselves and have seen many previous research efforts. Addressing both simultaneously is even more challenging, with many existing approaches focusing on one over another. In this paper, we propose the Reduced Colored Petri Net (RCPN) model that has two advantages: first, it offers a very simple and intuitive way of modeling pipelined processors; second, it can generate high performance cycle-accurate simulators. RCPN benefits from all the useful features of Colored Petri Nets without suffering from their exponential growth in complexity. RCPN processor models are very intuitive since they are a mirror image of the processor pipeline block diagram. Furthermore, in our experiments on the generated cycle-accurate simulators for XScale and StrongArm processor models, we achieved an order of magnitude (~15 times) speedup over the popular SimpleScalar ARM simulator. Comment: Submitted on behalf of EDAA (http://www.edaa.com/)

Abstract

Submitted on behalf of EDAA (http://www.edaa.com/); International audience; While most of the effort in improving verification times for pipeline machine verification has focused on faster decision procedures, we show that the refinement maps used also have a drastic impact on verification times. We introduce a new class of refinement maps for pipelined machine verification, and using the state-of-the-art verification tools UCLID and Siege we show that one can attain several orders of magnitude improvements in verification times over the standard flushing-based refinement maps, even enabling the verification of machines that are too complex to otherwise automatically verify.