ARAS: asynchronous RISC architecture simulator

Abstract

In this paper, an asynchronous pipeline instruction simulator, ARAS is presented. With this simulator, one can design selected instruction pipelines and check their performance. Performance measurements of the pipeline configuration are obtained by simulating the execution of benchmark programs on the machine architectures developed. Depending on the simulation results obtained by using ARAS, the pipeline configuration can be altered to improve its performance. Thus, one can explore the design space of asynchronous pipeline architectures.

Original document

The different versions of the original document can be found in:

• https://openscholarship.wustl.edu/cgi/viewcontent.cgi?article=1363&context=cse_research

• http://xplorestaging.ieee.org/ielx3/3937/11406/00514658.pdf?arnumber=514658,

http://dx.doi.org/10.1109/wcadm.1995.514658

• https://openscholarship.wustl.edu/cse_research/363,

https://dblp.uni-trier.de/db/conf/async/async1995.html#ChienFPP95,

https://openscholarship.wustl.edu/cgi/viewcontent.cgi?article=1363&context=cse_research,

https://ieeexplore.ieee.org/document/514658,

https://academic.microsoft.com/#/detail/2107187484