Abstract

This paper proposes a reconfigurable pipelined multiplier architecture that achieves high performance and very low energy dissipation by adapting its structure to computational requirements over time. In this reconfigurable multiplier energy is saved by disabling and bypassing an appropriate number of pipeline stages whenever input data rates are low. To evaluate the efficiency of our multiplier architecture, we have designed a multiplier-based inverse quantizer (IQ) for MPEG-2 MP@ML. Pipelines are dynamically reconfigured according to the size of the picture and the number of nonzero quantized DCT coefficients per block. In comparison with corresponding multiplier implementations that use conventional pipelines, our reconfigurable multipliers dissipate about 31-58% less energy. Relative energy savings increase with decreasing data rates, since our reconfigurable structures stay in a low energy configuration for proportionately longer time.


Original document

The different versions of the original document can be found in:

http://dx.doi.org/10.1109/iwv.2000.844541
https://academic.microsoft.com/#/detail/2148919406


DOIS: 10.1109/iwv.2000.844541 10.21236/ada393140

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Document information

Published on 06/11/02
Accepted on 06/11/02
Submitted on 06/11/02

Volume 2002, 2002
DOI: 10.1109/iwv.2000.844541
Licence: CC BY-NC-SA license

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