Clocked and asynchronous instruction pipelines

Abstract

Clocked (synchronous) and self-timed (asynchronous) methodologies represent the two principal design approaches associated with timing control and synchronization of digital systems. In the paper, clocked and asynchronous instruction pipelines are modeled and compared. The approach which yields the best performance is dependent on technology parameters, operating range and pipeline algorithm characteristics. Design curves are presented which permit selection of the best approach for a given application and technology environment.

Original document

The different versions of the original document can be found in:

• https://openscholarship.wustl.edu/cgi/viewcontent.cgi?article=1321&context=cse_research

• http://xplorestaging.ieee.org/ielx2/937/7000/00282753.pdf?arnumber=282753,

http://dx.doi.org/10.1109/micro.1993.282753

• https://openscholarship.wustl.edu/cse_research/321,

https://dl.acm.org/citation.cfm?id=255282,

https://dblp.uni-trier.de/db/conf/micro/micro1993.html#FranklinP93,

https://openscholarship.wustl.edu/cgi/viewcontent.cgi?article=1321&context=cse_research,

https://ieeexplore.ieee.org/document/282753,

https://academic.microsoft.com/#/detail/2145874611