Abstract
lication-specific instruction set processor (ASIP) design is a promising technique to meet the performance and cost goals of high-performance systems. ASIPs are especially valuable for embedded computing (e.g., digital cameras, color printers, cellular phones, etc.) where a small increase in performance and decrease in cost can have a large impact on a product's viability. Sutherland, Sproull, and Molnar have proposed a processor organization called the counterflow pipeline (CFP) that is appropriate for ASIP design due to its simple and regular structure, local control and communication, and high degree of modularity. This paper describes a new CFP architecture, called the wide counterflow pipeline (WCFP) that extends the original proposal to be better suited for custom embedded instruction-level parallel processors. This work presents a novel and practical application of the CFP to automatic and quick turn-around design of ASIPs. The paper introduces the WCFP architecture and describes several microarchitecture enhancements needed to get good performance from custom WCFPs. We demonstrate that custom WCFPs have performance that is up to four times better than that of ASIPs based on the original CFP.
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Published on 01/01/2002
Volume 2002, 2002
DOI: 10.1109/pact.2000.888331
Licence: CC BY-NC-SA license
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